IETE TECHNICAL REVIEW https://doi.org/10.1080/02564602.2021.1960903 Low and High V t GOTFET Devices Outperform Standard CMOS Technology in Ternary Logic Applications Ramakant Yadav , Surya Shankar Dan and Simhadri Hariprasad Dept. of Electrical & Electronics Engineering, Birla Institute of Technology and Science Pilani, Hyderabad Campus, Hyderabad, India ABSTRACT This work reports low and high threshold gate-overlap tunnel FET (GOTFET) devices for ternary logic applications. An iterative numerical algorithm was developed, which optimises the GOTFET struc- ture such that its characteristics are far superior to the equally-sized MOSFET at the same technology node. These devices are designed in such a way that the low and high V t (LVT & HVT) are V tl = V dd /3 and V th = 2V dd /3 respectively, with the ranges (0 ··· V dd /3), (V dd /3 ··· 2V dd /3) & (2V dd /3 ··· V dd ) rep- resenting 0, 1 & 2 states respectively. The performance of the GOTFETs is explained with physical explanations and models of device operation. Optimised GOTFETs were benchmarked with standard MOSFETs for the same circuits designed using the same technology. We have used 45 nm technol- ogy for all benchmarking purposes, since it is the lowest industry-standard technology library freely available for academic purposes. Proposed GOTFETs have on currents I on roughly twice, and off cur- rents I off at least an order lower than the corresponding MOSFETs. Furthermore, this work proposes a method to effectively suppress the ambipolar behaviour of GOTFETs with improved device perfor- mance, engineering the appropriate drain doping concentration, and a gate overlap/underlap on the source and drain regions. The performance of the optimised complementary GOTFET (CGOT) negative ternary inverter (NTI), positive ternary inverter (PTI) & standard ternary inverter (STI) cells were benchmarked with equivalent CMOS circuits. The overall PDP of the CGOT ternary cells were 99.9% lower than the corresponding CMOS cells. The proposed CGOT ternary cells will serve as the starting point for any ternary logic applications. KEYWORDS 45 nm CMOS technology; I on :I off ratio; Low & high V t (LVT & HVT); NTI; PTI and STI cells; Power delay product (PDP) 1. INTRODUCTION Ternary logic yields new functionalities in VLSI applica- tions, which are difcult to achieve through conventional CMOS based binary logic [1,2]. The primary require- ment of ternary logic is that the devices used to imple- ment them must have two distinct threshold voltages [3]. In this work, LVT & HVT gate-overlap TFET (GOTFET) devices have been introduced, which switch among logic states, 0, 1 & 2. Advantages of ternary logic: With the scaling of CMOS technology, interconnect delays in binary logic circuits that were once negligible compared to the transistor delays, have become more signifcant than the transistor delays [4]. The low density of logic states fundamentally limits the performance of binary logic, i.e., the amount of data that can be transmitted by every binary digit (or ‘bit’) having only two logic states (0, 1) over a given set of lines [5]. Therefore, it needs a large number of logic gates and transistors to reach the required data size. Besides, the integrated circuits require more interconnected wirings between the system components. In a modern VLSI cir- cuit, approximately 70% of the area is devoted to inter- connects, 20% to insulation, and only 10% to device [6], which exceedingly increases the complexity, both in design and manufacture. One ternary digit (or ‘trit’) with three logic states (0, 1, 2) can represent the equiva- lent of log 2 (3) = 1.58 bits. For instance, a ternary register with 20 trits represents 3 20 = 3,486,784,401 ≈ 3.25 Gbits of data. Meanwhile, a register of 20 bits represents only 2 20 = 1,048,576 = 1 Gbits of data. Thus, it is possible to transmit more information over the interconnections, requiring much fewer devices for a given data length. Thus, ternary logic becomes exceedingly efective in real- time data processing applications. Advantages of GOTFETs: At the nm-scale dimensions, subthreshold leakage becomes extremely detrimental for the device operation. Hence, researchers worldwide have become interested in the TFET technology, which replaces classical transport in the case of conventional MOSFET with quantum-mechanical band-to-band (BtB) © 2021 IETE