22 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 1, JANUARY 2007 Enhanced Electrostatics for Low-Voltage Operations in Nanocrystal Based Nanotube/Nanowire Memories Udayan Ganguly, Chungho Lee, Tuo-Hung Hou, and Edwin Chihchuan Kan, Member, IEEE Abstract—The metal nanocrystal (NC)/carbon nanotube (CNT) based nonvolatile memory has been proposed recently in compar- ison to the microfabricated Si channel and Si NCs in ultranarrow channel structure. The electrostatics of metal NC-CNT devices during memory operations differ significantly from the metal NC memory with planar silicon channel. In this paper, we present the theoretical analysis on the three-dimensional (3-D) electrostatics of the NC-CNT device during memory operations, to illustrate the experimentally observed large number of charge storage at low gate bias (5 V) despite a 100-nm-thick bottom-gate control dielectric. NCs are electrostatically more strongly coupled to the two-dimensional (2-D) gate electrode than to the one-dimensional (1-D) channel, even when the NCs are in much closer proximity to the 1-D channel, for efficient tunneling and low-voltage program operation. Under the retention condition, the NC-CNT devices have lower electric field across tunneling oxide than that in the case of a 2-D channel. This increasing electric field difference with respect to program versus retention operations indicates larger ratio between program and retention times. Together with the large number of electrons stored per NC, this enhanced electro- statics can be utilized either to reduce the operating voltage or to reduce statistical fluctuation of the information storage. Index Terms—Carbon nanotube (CNT), electrically erasable programmable read-only memory (EEPROM), electrostatics, field effect transistor, nanocrystal (NC), nonvolatile memories. I. INTRODUCTION I N COMPARISON with dynamic random-access memory (DRAM), electrically programmable erasable read-only memory (EEPROM) has significant advantages on geomet- rical scaling due to its one-transistor cell and current readout mechanism. For EEPROM, low voltage operation, power scaling, and enhanced retention/program time ratio are the main challenges in technology scaling. Discrete nanoscale floating gates by semiconductor and metal nanocrystals (NCs) have been proposed to replace the thin-film floating gate for reliable tunneling oxide scaling in low voltage operations [1]–[5]. A similar device with charge stored in Si N traps rather than NCs has also been explored extensively [6]. Metal Manuscript received December 10, 2005; revised August 22, 2006. This work was supported by the Center for Nanoscale Systems (CNS), Cornell University, from the NSF Engineering Directorate. The review of this paper was arranged by Associate Editor T. Hiramoto. U. Ganguly was with the Department of Materials Science and Engineering, Cornell University, Ithaca, NY 14853 USA. He is now with the Applications Development Center, Front End Products, Applied Materials, Sunnyvale, CA 94085 USA (e-mail: ug23@cornell.edu). C. Lee was with the School of Electrical and Computer Engineering, Cornell University, Ithaca, NY 14853 USA. He is now with the Nonvolatile Memory Technology Development Group, Spansion LLC, Sunnyvale, CA 94088 USA. T.-H. Hou and E. C. Kan are with the School of Electrical and Computer Engineering, Cornell University, Ithaca, NY 14853 USA. Digital Object Identifier 10.1109/TNANO.2006.888529 Fig. 1. Basic NC-CNT memory schematic showing: (a) bottom-gate and (b) top-gate structures. NCs have advantages over semiconducting NCs or traps from both electrostatic (larger electric field focusing) and transport perspectives (larger density of states) [2]–[4]. High-k dielectrics have been used to replace SiO in the tunneling and control dielectrics [4], [5] to further optimize the tunneling barrier and electrostatics. Another important structural variation has been the ultranarrow sensing channel, where sub-10 nm cross-sec- tional channels have been fabricated in silicon-on-insulator (SOI) structures [7], [8] to obtain high charge sensitivity and reliability. Memory cells with carbon nanotube (CNT) as the sensing channel and Si N traps as charge-storage nodes have also been reported [9]. Recently, memory cells based on metal NC and CNT have been demonstrated with further improved characteristics [10] despite a 100 nm bottom-gate control dielectric. The channel transport in NC-CNT memories has been modeled by the nonequilibrium Green’s functions (NEGF) in the presence of charges stored in the NC [11]. In this paper, we theoretically explore the NC-CNT memory from the three-dimensional (3-D) electrostatics perspective, in an attempt to establish the principle for low voltage operations. This analysis further illustrates the significant advantages of this structure over planar Si channels. II. THE ELECTROSTATIC MODEL The basic bottom-gate (BG) and top-gate (TG) memory struc- tures are shown in Fig. 1, following the experimental device de- sign in [10]. The bottom-gate device consists of a CNT on top of thermal SiO grown on the degenerately doped Si substrate that acts as a gate electrode. The CNT is then covered by the tun- neling dielectric of 4 nm thickness, and followed by metal NCs self-assembly. A 30 nm thick SiO passivates the entire device. The top-gate memory structure has a similar process except that 1536-125X/$25.00 © 2007 IEEE