IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 12, DECEMBER 2005 2697 Nonvolatile Memory With a Metal Nanocrystal/Nitride Heterogeneous Floating-Gate Chungho Lee, Tuo-Hung Hou, and Edwin Chih-Chuan Kan, Member, IEEE Abstract—Heterogeneous floating-gates consisting of metal nanocrystals and silicon nitride Si N for nonvolatile memory applications have been fabricated and characterized. By com- bining the self-assembled Au nanocrystals and plasma-enhanced chemical vapor deposition (PECVD) nitride layer, the heteroge- neous-stack devices can achieve enhanced retention, endurance, and low-voltage program/erase characteristics over single-layer nanocrystals or nitride floating-gate memories. The metal nanocrystals at the lower stack enable the direct tunneling mech- anism during program/erase to achieve low-voltage operation and good endurance, while the nitride layer at the upper stack works as an additional charge trap layer to enlarge the memory window and significantly improve the retention time. The write/erase time of the heterogeneous stack is almost the same as that of the single-layer metal nanocrystals. In addition, we could further en- hance the memory window by stacking more nanocrystal/nitride heterogeneous layers, as long as the effective oxide thickness from the control gate is still within reasonable ranges to control the short channel effects. Index Terms—Direct tunneling, nanocrystal/nitride heteroge- neous floating-gate, nonvolatile memories. I. INTRODUCTION T HE conventional charge storage-based Flash memory has remained in the lead in the nonvolatile memory market segment, but new device technologies have become more competitive [1]. Continuous scaling for higher density and lower voltage operation keeps pushing the search for better operational principles and device designs. Recently, new materials and structures of the gate stack in Flash have been widely studied. Discrete floating-gate memories, such as nanocrystal [2], [3], and silicon–oxide–nitride–oxide–sil- icon (SONOS) [4], [5] memories, are among the promising approaches. Local charge storage in discrete memory nodes enables more aggressive scaling of the tunneling oxide by relieving the total charge loss concern of the continuous floating-gate. Nanocrystal memories with ultrathin ( 3 nm) tunneling oxide can promise low-voltage operation, fast pro- gram/erase (P/E) time, and good endurance characteristics through direct tunneling charging/discharging mechanisms. Manuscript received May 4, 2005; revised August 25, 2005. This work was supported by the National Science Foundation (NSF). The review of this paper was arranged by Editor R. Singh. C. Lee is with Spansion, LLC, Sunnyvale, CA 94085 USA (e-mail: cl249@cornell.edu). T.-H. Hou and E.C. Kan are with the School of Electrical and Computer En- gineering, Cornell University, Ithaca, NY 14853 USA . Digital Object Identifier 10.1109/TED.2005.859615 However, the thin oxide is not a sufficient leakage barrier and results in the retention degradation. SONOS, on the other hand, have a better retention characteristic by storing charges in the distributed deep traps of the nitride layer. However, high oper- ational voltage, difficult trap control, operational fluctuations, and low sheet charge density remain challenging for large-scale production. Heterogeneous stacks of multiple floating-gate layers have emerged as a possibility to take the best properties from each floating-gate choice [6]–[8], where long retention and short P/E time had been experimentally demonstrated in comparison with a single storage layer. The detailed physical mechanisms and design principles in the heterogeneous stack are not yet clear. Possible observations include Coulomb blockade be- tween the heterogeneous storage nodes [8], inefficient inelastic tunneling in the retention condition, and detailed control of the band misalignments [6], [7]. Semiconductor nanocrystal (Si) and nitride heterogeneous stacks have been first proposed in metal–nitride–oxide–silicon (MNOS) structure by Yamazaki et al. [9], [10] and SONOS structure by Steimle et al. [6], [7]. In this paper, we propose heterogeneous stacks containing metal nanocrystals and nitride, which can offer even better memory characteristics. The lower metal nanocrystal layer offers large charge storage capacity, tunable work function, and high density of available states that enables stable operations independent of trap annealing [8]. Charge injection across the direct tunneling oxide to the intermediate metal nanocrystal layer results in low-voltage P/E and good endurance. The upper nitride layer as an additional memory node through Poole–Frenkel (PF) or Fowler–Nordheim (FN) charge transport provides deep distributed potential well for longer retention and a larger memory window. II. DEVICE FABRICATION A standard CMOS front-end process except for the addition of nanocrystal/nitride floating-gate formation was adopted for the device fabrication [8]. The single and double heterogeneous stack floating-gate structures are shown in Fig. 1. The gate stack formation was performed in the active areas which were defined by 1- m local oxidation of silicon (LOCOS) on p-type (100) Si substrates. The tunneling oxide was thermally regrown by trichloroethane (TCA) dry oxidation at 750 C for 10 min with a subsequent annealing in inert ambient for up to 900 C. To ensure direct tunneling for write/erase, the tunneling oxide thickness was controlled in the direct tunneling 0018-9383/$20.00 © 2005 IEEE