A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology Hooman Farkhani a , Ali Peiravi a , Farshad Moradi b,n a Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran b Integrated Circuits and Electronics Laboratory (ICE-LAB), Department of Engineering, Aarhus University, Denmark article info Article history: Received 26 January 2014 Received in revised form 20 August 2014 Accepted 11 September 2014 Available online 11 October 2014 Keywords: SRAM Write Margin Read Static Noise Margin CMOS abstract A new asymmetric 6T-SRAM cell design is presented for low-voltage low-power operation under process variations. The write margin of the proposed cell is improved by the use of a new write-assist technique. Simulation results in 65 nm technology show that the proposed cell achieves the same RSNM as the asymmetric 5T-SRAM cell and 77% higher RSNM than the standard 6T-SRAM cell while it is able to perform write operation without any write assist at V DD ¼1 V. Monte Carlo simulations for an 8 Kb SRAM (256 Â 32) array indicate that the scalability of operating supply voltage of the proposed cell can be improved by 10% and 21% compared to asymmetric 5T- and standard 6T-SRAM cells; 21% and 53% lower leakage power consumption, respectively. The proposed 6T-SRAM cell design achieves 9% and 19% lower cell area overhead compared with asymmetric 5T- and standard 6T-SRAM cells, respectively. Considering the area overhead for the write assist, replica column and the replica column driver of 2.6%, the overall area reduction in die area is 6.3% and 16.3% as compared with array designs with asymmetric 5T- and standard 6T-SRAM cells. & 2014 Elsevier Ltd. All rights reserved. 1. Introduction CMOS technology has been the cornerstone of semiconductor devices for years. Moore's law predicts technology down scaling that leads to improvements in performance features such as speed, power consumption and area. Although circuits and systems benefit from technology down scaling in some aspects, the undesired features such as short channel effects (SCEs) and sensitivity to process variations are also consequential. The effect of process variations on performance is a key issue in scaled CMOS technology. This effect gets more pronounced as the size of transistors is reduced. One of the highly sensitive circuits to process variations is SRAM that is due to the use of small devices in order to achieve a higher density. Process variations can be due to global or local mismatches between devices. Global variation refers to die-to-die variations in devices and local mismatch refers to mismatch between transistors on the same die [1]. Local mismatch in SRAM devices can easily lead to read stability degradation (stored data is flipped during read), read failure (data is not read during read period), writeability decrease or write time increase. Besides, improving the write features of the SRAM leads to degradation in its read performance and vice versa. Fig. 1 shows the standard 6T-SRAM cell structure. It consists of two back to back inverters (PUL–PDL and PUR–PDR) which keep the data and its inverse on nodes Q and QB, respectively. The access transistors (ACL–ACR) are used to perform read and write operations. Due to using a common path (ACL–ACR) for read and write, improving read stability will lead to degradation of writeability of the cell and vice versa. To improve the Read Static Noise Margin (RSNM) of an SRAM cell, beta ratio (β ¼ W PD /W AC ) can be increased, while a lower alpha ratio (α ¼ W PU /W AC ) is desirable to improve the cell writeability. Finally, during hold mode, equal strength for pull up and pull down transistors sets the trip point of the two back-to-back inverters at V SUPPLY /2 and ensures maximum noise margin. Several solutions have been proposed in the literature from device to architecture levels to improve SRAM cell functionality. For instance, at device level, using new devices such as FinFETs leads to significant SRAM performance improvement [1–4]. At cell level, new cells such as 7T, 8T, 9T,10T, and 11T [5–11] have been proposed that come with a penalty in area overhead while other proposed cells such as asymmetric 6T and 5T topologies [12,13] occupy the same area compared to the standard symmetric 6T SRAM cell. At architecture level, read and write assist techniques improve SRAM robustness and performance while they occupy Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/mejo Microelectronics Journal http://dx.doi.org/10.1016/j.mejo.2014.09.006 0026-2692/& 2014 Elsevier Ltd. All rights reserved. n Corresponding author. E-mail addresses: Farkhani.hooman@stu.um.ac.ir (H. Farkhani), Peiravi@um.ac.ir (A. Peiravi), moradi@eng.au.dk (F. Moradi). Microelectronics Journal 45 (2014) 1556–1565