Realization of both a single electron transistor and a field effect transistor with an underlapped FDSOI MOSFET geometry Benoˆ ıt Roche ∗ , Benoit Voisin ∗ , Xavier Jehl ∗ , Marc Sanquer ∗ , Romain Wacquez † , Maud Vinet † , Veeresh Deshpande † and Bernard Previtali † ∗ CEA, INAC, SPSMS, 17 rue des Martyrs, F-38054 GRENOBLE Cedex 9 Email: xavier.jehl@cea.fr † CEA, LETI, MINATEC Campus, 17 rue des Martyrs, F-38054 GRENOBLE Cedex 9 Abstract—A dual mode device has been realized with FD- SOI MOSFET technology implementing both a single electron transistor (SET) and a field effect transistor (FET). The silicon substrate is used as a back gate to choose between these two functionalities. We show in this paper that the behavior of the device is determined by the position of the electron gas in the silicon mesa: the device is a SET if the electron gas is created by the top gate, and behaves as a FET when the back gate induces a electron gas at the bottom of the silicon mesa. This opens the possibility to design hybrid circuits exploiting both advantages of FETs and SETs. Index Terms—FDSOI, single electron transistor, silicon-on- insulator, nanoelectronics I. I NTRODUCTION Single electron transistors are promising devices to design electronic circuits with ultra-low power require- ments [1]. The mature silicon technology offers now the opportunity to realize such a device working up to room temperature [2]. Yet realizing complex circuits embedding SETs remains challenging. Such a circuit require FETs to work together with SETs on the same chip. Some real- izations have demonstrated coupled SET-FET circuits for multi-valued logic applications [3]. In this paper we show that we are able to design a device working either as a FET or as a SET depending only on a single gate voltage. It is obviously very convenient to have these two behaviors with the same device as it simplifies the fabrication processes. Moreover, because we used a semi-industrial foundry to re- alize the devices presented in this work all the technological steeps are compatible with CMOS technology. II. DEVICES DESCRIPTION The devices presented here are fabricated on 200 mm silicon-on-insulator wafers, with a 150 nm thick BOX. We will focus only on one single device in this paper, however many devices have been fabricated and show the same behavior. Devices consist of single gate MOSFETs adapted from FDSOI technology (see Fig. 1), with a slight modification of the source and drain modules. The active                      Fig. 1. TEM images of a device area and gate level are patterned with a hybrid UV/e-beam lithography which enable to design 20 nm gate lengths or mesa widths. A legacy polycrystalline silicon / SiO 2 (5 nm thick) gate stack is used instead of a high-k dielectric and metallic gate because it provides a much better stability at low temperature. The standard defect level of the current gate stack used in microelectronics induces shifts in the operation point of the device equivalent to some mV of the gate voltage. Such unwanted shifts, corresponding to the trapping of single electrons by an interface state, should be avoided in such devices which work on single electron effects. The silicon substrate of the wafer is used as a back gate. It provides the additional control parameter require to choose between SET and FET behaviors. Without back gate polarization (V bg = 0 V), the modified source and drain modules turn the field-effect-transistor into a single elec- tron transistor at low temperature, as reported before [4]. The main difference as compared to conventional FDSOI MOSFETs consists in increasing the underlapped region of the transistor. This is done by forming silicon nitride spacers on both sides of the gate. A high As doping is used to create source and drains contacts with a final concentration above 10 20 cm -3 . The spacers prevent the silicon mesa underneath from being doped. This undopped region act as a access resistance to the channel, and is responsible for the SET 978-1-4673-0192-3/12/$31.00 ©2012 IEEE 129