A DYNAMIC RECONFIGURABLE FABRIC FOR PLATFORM SOCS C. Papachristou, J. Weaver, R. Vijayakumar and F. Wolff Department of Electrical Engineering and Computer Science Case Western Reserve University Cleveland, Ohio 44106 1. ABSTRACT A dynamic coarse-grained reconfigurable architecture which tar- gets computationally intensive applications like multimedia and wireless applications is presented. Fundamental features of the architecture are an interconnection matrix, switch buffers, func- tional units, and a controller. Important aspects of the architec- ture is dynamic datapath reconfiguration over each control step of the application. Simulations of several classes of applica- tions with results are also presented. Results of Xilinx Virtex 4 Implementations are provided. 2. INTRODUCTION & MOTIVATION Motivation. VLSI chip functionality has traditionally concen- trated into two device categories, microprocessor and ASIC (Ap- plication Specific Integrated Circuits). ASICs have high perfor- mance but are rigid addressing a specific application, whereas microprocessors are flexible for general-purpose applications. A third category, FPGAs (Field Programmable Logic Arrays) provide, through programmable logic, good flexibility but lower performance. However, present system on chip (SOC) technol- ogy pulls together ASICs, microprocessors and FPGAs into a single polymorphic multiple core chip design. SOC technol- ogy is well suited for many new compute-intensive applica- tions such as signal and image processing, visualization, wire- less communications, and networking. There is an important need for reconfigurable hardware in future SOC applications. For example, SOC products will be wireless communicating with powerful servers for applications. Opti- mizing performance while maintaining low power consumption will depend on the SOC ability for quick or even dynamic re- configuration. There are two emerging trends for SOC configurability. a) Platform FPGAs which integrate into a large FPGA structure microprocessor cores, ASIC blocks (e.g. hardwired multipliers) and memories. b) Platform SOC integrating microprocessor, ASICs and memory cores but also reconfigurable hardware fab- rics. Platform FPGAs are reconfigured using the FPGA struc- ture; however, configuration of Platform SOCs can be done by the reconfigurable hardware. Platform FPGAs have the advan- tage of platform stability, but they are tied to the vendor’s offer- ings. It appears that Platform SOC fabrics are more suitable for implementing multiple core systems because they are more flex- ible, potentially can consume less power, and are amenable to dynamic or even autonomous reconfiguration. In such an envi- ronment, a reconfigurable datapath core could be driven to data intensive applications whereas a microprocessor core to other functions. Contribution. In this paper we present a new coarse grain re- configurable architecture fabric based on a switch buffer matrix connecting functional unit blocks that operate in parallel. The fabric is well suited for integration into a platform SOC of a multicore system, particularly to accelerate computation inten- sive applications. The fabric is scalable in terms of functional units but also at the bit level in that functional units can be bit- sliced using and connected through the same switch matrix. We also present a design synthesis technique for mapping applica- tions into the reconfigurable fabric. The mapping has been im- plemented and tested using several High Level Synthesis tools as well as new tools we developed. We have prototyped our architecture into the Xilinx Virtex IV platform, including simu- lation and implementation of benchmark applications. 3. RECONFIGURABLE ARCHITECTURE The basic idea of the reconfigurable fabric is a distributed set of programmable processing tiles that are capable of instantaneous dynamic reconfigurability, Fig. 1. A tile consists of three types of hardware units or resources, i.e. functional unit, a distributed switch buffer matrix, and local control unit. All hardware re- sources are connected together through a loop of bus-line inter- connects. The functional units are configurable to perform ba- sic arithmetic/logic functions such as Add, Subtract, Multiply. The controller is normally fine grain so it can be implemented using conventional FPGA technology. The routing of data be- tween the switch buffers and functional units are carried out by the switch buffer matrix, e.g. a sort of cross bar, which is em- bedded in the tile. A programmable tile goes much beyond the current FPGA technology. A tile achieves a middle grain con- figuration by efficiently allocating its resources, i.e. functional units and switch buffers as well as their interconnects. Configu- ration occurs within a tile and along several tiles, which can be interconnected into a reconfigurable fabric. Basically, tiles are suitable for efficiently implementing ap- plication function modules such as the FIR filter, FFT, DCT and convolution coder. There are two related problems that have been addressed in this research: (i) mapping a function mod- ule into a tile; (ii) reconfiguring dynamically a tile for another function module. For the mapping problem, we propose to use the following 2-phase design process: a) data flow transforma- tion of the function description (e.g. C code) into a resource scheduled graph, b) allocation of data flow elements into the tile hardware resources (operators, cache and interconnects, Fig. 1).