Vol.:(0123456789) 1 3 Applied Physics A (2020) 126:487 https://doi.org/10.1007/s00339-020-03616-0 Implementation of digital‑to‑analog converter through CP‑based GaAs/GaSb nanowire GAA‑TFET Anil Lodhi 1  · Chithraja Rajan 1  · Dheeraj Sharma 1  · Amit Kumar Behera 1  · Dip Prakash Samajdar 1  · Atul Kumar 1 Received: 23 November 2019 / Accepted: 8 May 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020 Abstract Digital-to-analog converter (DAC) is the most critical circuit of any chip which limits system performance and consume much power. Therefore, the focus of this work is the DAC implementation using GaAs/GaSb-based charge plasma nanow- ire GAA-TFET which provide better ON current at reduced ambipolarity and hence, reduce power consumption. Also, the linearity of the proposed device is much better than Si TFET due to the absence of random dopant fuctuation and hence, improves DAC accuracy. The DAC implemented here is the R–2R and current steering architecture which is the frst ever known work of a charge plasma-based hetero-material nanowire TFET. For the DAC implementation, Verilog A lookup table is created from the simulated results of this device from TCAD Silvaco and rest of the circuit simulation is carried out in Cadence. Finally, DAC performance metrics have been analyzed and found that efciency of current steering has been drastically improved compared to R–2R architecture. Keywords Nanowire · GAA  · TFET · Charge plasma · Hetero-material · High K dielectric · DAC 1 Introduction CMOS has reached to the extend where short channel efects (SCE’s) [1] has become bottleneck for the developing resource constraint electronic industry. Limited subthreshold swing (SS) and OFF-state leakage current suppress CMOS scaling beyond 40 nm. These limitations motivated arise of novel semiconductor devices for low power applications. One such boom is tunnel FET (TFET) [2]. TFET stood its separate place in low power devices as such its SS is not limited to 60 mV/dec and very low of current [3]. However, the lack of sufcient on current and high ambipolarity in Si TFET restricted its exposure in circuit applications. Nev- ertheless, many researchers had focused to improve TFET characteristics, but their utilization in circuits is ceased because of the absence of novel device model fles. There- fore, in this paper, we are introducing a high performing low power charge plasma (CP)-based GaAs/GaSb nanowire gate all around tunnel FET (GaAs/GaSb-NW-GAA-TFET) for digital-to-analog Converter (DAC) for the frst time. CP creates pseudo source and drain regions through metal work function engineering which avoid any specifc regional dop- ing. Therefore, CP devices are immune to random process variations and produce accurate results, which provide bet- ter ON current at reduced ambipolarity and hence, reduce power consumption. Indeed, highly linear device are the uttermost importance for converters. Therefore, the proposed CP-based device, which avoid sharp doping boundaries and junctions, shows considerable improvement in linearity as compared to Si TFET is proved to be a good choice for fault- free DAC architecture. The DAC [4] is a system that reconstructs an analog waveform according to a digital word input. The informa- tion transmitted through wireless is digital, but the signals * Anil Lodhi lodhianil011@gmail.com Chithraja Rajan rajan.chithraja@gmail.com Dheeraj Sharma dheeraj24482@gmail.com Amit Kumar Behera amitiiit12@gmail.com Dip Prakash Samajdar dipprakash010@gmail.com Atul Kumar atul.kumar@iiitdmj.ac.in 1 PDPM Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, Jabalpur 482005, Madhya Pradesh, India