Impact of quantum effects on the short channel effects of III–V nMOSFETs in weak and strong inversion regimes T. Dutta a,⇑ , Q. Rafhay a , R. Clerc a , J. Lacord b , S. Monfray b , G. Pananakakis a , F. Boeuf b , G. Ghibaudo a a IMEP-LAHC, Minatec Campus, 3 parvis Louis Néel, 38016 Grenoble, France b STMicroelectronics, 850, rue J. Monnet, BP. 16, 38921 Crolles, France article info Article history: Available online 9 May 2013 Keywords: Short channel effects III–V MOSFETs Quantum effects Dark space Generalized DIBL parameter abstract This paper investigates the impact of quantum effects on the increase of short channel effects in III–V MOSFETs. First of all, contrary to the results obtained by other groups [1,2], quantum confinement has been found to play no role on the short channel effects occurring in the subthreshold regime. In this regime, the main origin of the increase of SCEs is simply due to the higher dielectric constant of III–V semiconductors. However, in strong inversion regime, the increase of the electrical equivalent oxide thickness due to quantum confinement is shown to have a detrimental impact on the drain induced bar- rier lowering. These results further confirm that III–V technologies will require innovative devices like ultra-thin films or multi-gate structures to ensure a better control short channel effects. Ó 2013 Elsevier Ltd. All rights reserved. 1. Introduction The replacement of silicon as channel material by III–V semi- conductors has emerged as a realistic option for the end of the roadmap of CMOS [3]. Indeed, these materials present greatly im- proved transport properties with respect to unstrained or strained silicon [4]. Many experimental results have already been published and recently, Radosavljevic et al. [5] have presented a tri-gate III–V structure showing promising performances, especially regarding the control of short channel effects (SCEs) control. Simulations and experimental results have shown that III–V technologies are subject to enhanced short channel effects, includ- ing larger V t -roll Off, larger drain induced barrier lowering and sub- threshold slope than the silicon devices [5–8], which might compromise their use for the end of the roadmap of CMOS devices [9]. In particular references [6,7] have shown by numerical simula- tion and analytical modeling that the subthreshold slopes of Ge and III–V MOSFET were larger than in Si, and [8] has demonstrated that In 0.7 Ga 0.3 As Quantum Well FETs present poor scalability for the same reason. In addition to the increased SCEs, it has been shown by the mean of simulation that quantum confinement in III–V channel is enhanced [10,11]. Indeed, due to the smaller effective masses and hence the smaller the density of states (DOS) of these semiconduc- tors, a larger degradation of the gate coupling with the channel is expected with respect to silicon channel [12]. This effect is shown to result in an increased electrical Equivalent Oxide Thickness (EOT) with respect to the physical oxide thickness, phenomenon also called dark space [10–13]. Recently published results [1,2] have stated that they could im- pact the short channel effects in the subthreshold regime. How- ever, these results are questionable as the approach used in these works consists in comparing a classical simulator, an analytical model based on Poisson–Schrödinger fitting and quantum cor- rected TCAD simulation. These codes comparisons are known to show some significant divergences and should be carried out with care, as done in reference [14] for different quantum confinement codes or in [15] for different codes of transport in nanoscale nMOSFET. Moreover, SCEs have been shown to have a detrimental impact on inverter performances in the strong inversion regime. Indeed, it has been shown in [16,17] that the SCEs in strong inversion regime, and especially the non saturation of the drain current caused by the Drain Induced Barrier Lowering (DIBL) could severely degrade the delay and propagation time of inverter and ring oscillator. Therefore, a comprehensive evaluation of the impact of SCEs in III–Vs should not be limited to the subthreshold regime only, as carried out in [6–8], but should also include strong inversion. In this regime however, the impact of quantization on the inversion charge is no longer negligible, which raises the question of role of quantum effect on the DIBL in strong inversion. Two questions hence still remain open: 1/Do quantum effects impact the short channel effects in the subthreshold regime? 2/Do quantum effects impact the DIBL in the strong inversion regime? Therefore, Section 3 of this work will investigate of the SCEs in sub- threshold regime, with and without quantum effects. Section 4 will then presents the role quantum effects on the DIBL in strong inver- sion regime. 0038-1101/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2013.04.007 ⇑ Corresponding author. E-mail address: tapas.dutta@minatec.inpg.fr (T. Dutta). Solid-State Electronics 88 (2013) 43–48 Contents lists available at SciVerse ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse