MODELING AND SYNTHESIS OF A DYNAMIC AND PARTIAL RECONFIGURATION CONTROLLER S. Guillet*, F. de Lamotte*, N. Le Griguer*, ´ E. Rutten**, J.-P. Diguet*, G. Gogniat* *Lab-STICC, Universit´ e de Bretagne Sud, France, {sebastien.guillet,ﬂorent.lamotte, nicolas.le-griguer,jean-philippe.diguet,guy.gogniat}@univ-ubs.fr **LIG / INRIA Rh ˆ one-Alpes, France, eric.rutten@inria.fr ABSTRACT This paper presents a framework to integrate the formal syn- thesis of a reconﬁguration controller into a Model Driven Engineering methodology used for reliable design of recon- ﬁgurable architectures. This methodology is based on an extension of UML/MARTE, GASPARD, and the aforemen- tioned controller is obtained as a C code through a formal technique named Discrete Controller Synthesis. Taking ad- vantage of using both modeling and synthesis techniques, the approach demonstrates an effective reduction of com- plexity in the speciﬁcation of such reconﬁgurable systems. An application model of an image processing application is presented as a case study. 1. INTRODUCTION Designing adaptive Systems-on-Chip (SoC) has raised in complexity and sophistication over the last few years, and designing them to be safe is becoming even more complex. Even if adaptive systems became a reality with the introduc- tion of Dynamic and Partial Reconﬁguration (DPR) tech- nologies by Xilinx, autonomous reconﬁguration has not much been addressed. Designing correctness is an important issue in critical SoCs, as a single error can lead to a ﬁnancial, ma- terial and/or human disaster. However, adding reconﬁgura- tion concepts in such SoCs increases the design complexity as adaptive systems need to be both secure and optimized to address (often) contradictory constraints (i.e. quality of service, energy consumption, etc.). Many studies, including this one, are based on the hypothesis that the complexity will continue to increase, and thus the need in terms of model- ing and formal methodologies will become signiﬁcant. This is leading to a progressive usage of methodologies to apply abstraction and modeling techniques such as Model Driven Engineering (MDE) [1] and formal techniques to prove ex- ecution properties in these systems. MDE allows to specify a system both vertically (compilation ﬂow) and horizontally This work is supported by the ANR FAMOUS project (ANR-09-SEGI-003) (models for analysis, veriﬁcation, performance...). The pro- posed approach relies on such a methodology, starting from different models of the SoC, concerning its application, its architecture and association between software and hardware components. Properties about execution states and reconﬁg- uration possibilities are then extracted from these speciﬁca- tions to be used by a formal technique, which synthesizes the code of a controller. The role of the controller is to en- force these properties at runtime. Concerning the method- ology, this paper will focus especially on how to specify a Gaspard model in order to be ready for controller synthe- sis. Discrete Controller Synthesis (DCS) is the formal tech- nique chosen in this study to tackle the problem of complex- ity in the reconﬁguration speciﬁcation. After presenting the related work and tools, the control concepts are further de- tailed and ﬁnally, an example of a Gaspard model containing control information is shown. 2. RELATED WORK 2.1. Closed-loop control in reconﬁgurable architectures Many research works contribute to the domain of reconﬁg- urable embedded systems [2] [3], some of them use contin- uous control techniques. This study is especially interested in those which care about the closed-loop management of reconﬁguration. In [4], an FPGA-based PID motion control system that dynamically adapts the behavior of a robot is presented. Several designs can be swapped, and tradeoff be- tween them are evaluated in terms of area, speed or power consumption. It has to be noted that functional correctness of all the designs is veriﬁed by experiment, and not by a for- mal method. To assure the correctness of the execution of embedded systems, analysis veriﬁcation and control meth- ods are needed. These methods are often based on model checking, for example in [5] authors use such technique for migration (reconﬁguration) of algorithms from hardware to software. Another approach is based on theorem prov- ing, such as [6] that presents a framework for description and veriﬁcation of parametrized hardware libraries with lay- 978-1-4673-2256-0/12/$31.00 c 2012 IEEE 703