A computationally efficient model of single electron transistor for analog IC simulation Mohammed S. Radwan a,n , El-Said A. Marzouk a , Sameh E. Rehan b,1 , Abdel-Fattah I. Abdel-Fattah a a Communications and Electronics Engineering Department, Mansoura University, Egypt b Electrical Engineering department, Al-Imam Mohammad Ibn Saud Islamic University, Riyadh, Saudi Arabia article info Article history: Received 3 September 2014 Received in revised form 11 December 2014 Accepted 5 January 2015 Keywords: Tunnel junction (TJ) Single-electron transistor (SET) SIMON SECS Monte Carlo simulation Macro model Compact model Orthodox theory Master equation Thermionic current abstract A compact analytical single electron transistor (SET) model is proposed. This model is based on the “orthodox theory” of single electron tunneling, valid for unlimited range of drain to source voltage, valid for single or multi-gate, symmetric or asymmetric devices and takes the background charge effect into account. This model is computationally efficient in comparison with existing models. SET characteristics produced by the proposed model have been verified against Monte Carlo simulator SIMON and show good agreement. This model has been implemented in HSPICE simulator through its Verilog-A interface to enable simulation with conventional MOS devices and single electron inverter has been simulated and verified with SIMON results. At high operating temperature, the thermionic current is taken into account. & 2015 Elsevier Ltd. All rights reserved. 1. Introduction The single-electron transistor (SET) is one of the best candidates for future VLSI logic circuits because of its ultralow power dissipation, very small size, high switching speed and new functionalities [1–4]. It has unparalleled characteristics such as periodic increase and decrease of drain to source current with respect to gate voltage and increase of drain to source current as a function of drain voltage. Because of these unparalleled features of the SET in practical applica- tions, analysis of its behavior in circuits is important. There are three techniques to simulate single electron transistor: the Monte Carlo (MC) technique, SPICE macro-modeling technique, and compact analytical modeling technique. MC technique is the most popular approach that is used to simulate single electron devices. It starts with all possible tunneling events, calculates their probabilities, and uses the probabilities for weighting [5]. Tunnel events are considered to be independent and exponentially distributed. The main part of an MC simulator is the random number generator. Several MC simulators (i.e., SIMON [6], KOSEC [7], SENECA [8], MOSES [9], SECS [10], and an adaptive algorithm SEMSIM [11]) are developed to model single electron systems. These models are the most accurate way to simulate SET, but they cannot be used for large-circuit simulation because they are extremely time consuming and cannot simulate hybrid SET/MOS circuits. In SPICE macro-modeling technique, SET behavior is modeled using equivalent circuits based on conventional microelectronic components (such as voltage and current sources, diodes, and resistors). Few research efforts on macro-modeling of SET have been reported [12–14]. In compact analytical modeling technique, the steady state master equation is solved to calculate drain to source current. Various analytical models have been proposed for SET [15–22], each of them based on the orthodox theory. All of them except the model introduced in [18] have operating drain to source voltage limitation. In this paper, an analytical model for SET has been proposed. This model is based on the orthodox theory of single electron tunneling, valid for unlimited range of drain to source voltage. In master equation approach, the simulation time is linearly dependent on the number of charge states. The proposed model includes the minimum number of states to capture certain values of drain to source voltage. So, it is less time consuming than other models while maintaining a good agreement with SIMON results. It is applicable for single or multi-gate devices and the background charge effect is taken into consideration. At high operating temperature, the contribution of thermionic current is included in the proposed model. Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/mejo Microelectronics Journal http://dx.doi.org/10.1016/j.mejo.2015.01.003 0026-2692/& 2015 Elsevier Ltd. All rights reserved. n Corresponding author. E-mail address: saadradwan51@hotmail.com (M.S. Radwan). 1 Sabbatical leave from Mansoura University, Egypt started in Nov. 2014. Microelectronics Journal 46 (2015) 301–309