This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 1, JANUARY 2015 1 A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters Christophe Erdmann, Donnacha Lowney, Adrian Lynam, Aidan Keady, Member, IEEE, John McGrath, Edward Cullen, Daire Breathnach, Denis Keane, Patrick Lynch, Marites De La Torre, Ronnie De La Torre, Peng Lim, Anthony Collins, Brendan Farley, and Liam Madden Abstract—A reconfigurable heterogeneous 3D-IC is assembled from two 28 nm FPGA die with 580 k logic cells and two 65 nm mixed signal die on a 65 nm interposer in a 35 mm 2 CS-BGA package. One mixed signal die consists of sixteen 16 bit current steering DACs, the other die consists of sixteen 13 bit pipelined ADCs. The interposer provides optimal system partitioning; noise isolation and high density interconnect between subsystems. Receive SNDR > 61.6 dBFS to Nyquist at 500 MS/s and transmit SFDR > 63.8 dBc to 400 MHz at 1.6 GS/s is measured. Ultralow FPGA to converter die interface power of 0.3 mW/Gb/s is achieved and measured digital to analog isolation > 92dB. The solution can be dynamically optimized for channel count, power and speed. Index Terms—2.5D, 3D-IC, ADC, analog, CMOS, DAC, data converter, FPGA, heterogeneous, high performance, low power, re- configurable, SSI. I. INTRODUCTION I NTEGRATED circuit technology has evolved at an ex- ponential rate since the famous prediction of Moore. Technology scaling lowers the cost of memory and logic and has been the key driver behind monolithic integration. How- ever, analog, logic and memory manufacturing processes are not converging. Finer process geometries compromise high performance analog systems due to the familiar issues of lower power supply voltage for an almost constant threshold voltage, lower intrinsic device gain and increased contributions from parasitic elements. Heterogeneous systems that integrate mul- tiple different die, each using its own optimized technology, in a single package are now emerging in the ‘More than Moore’ landscape. A representative example is the 400 Gb/s networking line card memory system discussed in [1]. Data converters are required to interface digital processing engines, for example FPGAs, to the real world. Typically, dis- crete data converters are used and interfaced to the FPGA using Manuscript received April 22, 2014; revised July 09, 2014; accepted August 20, 2014. This paper was approved by Guest Editor Yogesh Ramadass. C. Erdmann, D. Lowney, A. Lynam, A. Keady, E. Cullen, D. Breathnach, D. Keane, P. Lynch, M. De La Torre, R. De La Torre, P. Lim, A. Collins, and B. Farley are with Xilinx, Saggart, Co. Dublin, Ireland. J. McGrath is with Xilinx, Little Island, Cork, Ireland. L. Madden is with Xilinx, San Jose, CA 95124 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2014.2357432 various IO standards such as LVDS or JESD204B. The expo- nential growth in wireless and wireline bandwidth requirements has mandated increased channel count, higher data converter sample rate and resolution. The digital interface is becoming a limiting factor in the system budget with respect to interconnect complexity and associated power. LVDS and JESD204B have associated interface power of approximately 25 mW/Gb/s. The integration of flexible data converters with FPGA eliminates this IO cost and also offers a dynamically scalable, power effi- cient platform solution that addresses diverse application needs. In this paper, our previously published work [2] is extended and a system is demonstrated with an aggregate bandwidth in excess of 400 Gb/s using sixteen 16 bit DAC instances running at 1.6 GS/s with an FPGA-to-die interface power of 0.3 mW/Gb/s. A reconfigurable receive system is introduced that allows channel count to trade with system sample rate. Specifically, a 500 MS/s ADC is demonstrated by interleaving four 125 MS/s units. Finally, the system is configured to realise a single channel millimetre wave wireless backhaul modem. Section II introduces the overall chip architecture and out- lines the system level considerations. Section III describes the logic capabilities. Sections IV and V discuss the data converter designs in relation to the system context. Particular attention is placed on the DAC design as it clearly highlights mixed signal design considerations in a 3D-IC environment. Mea- surement details and a comparison with previously published data comprise Section VI. Finally, Section VII summarizes the conclusions. II. CHIP ARCHITECTURE An overview of the chip architecture is depicted in Fig. 1 and a chip photograph is shown in Fig. 2. In total four die have been integrated into a single package using the Stacked Silicon Interconnect (SSI) technology [3]. There are two 65 nm analog die, one containing sixteen 125 MS/s 13 bit ADCs and the other sixteen 1.6 GS/s 16 bit DACs. The two 350T FPGA slices are processed in 28 nm. A. Data Converters Each mixed-signal die was divided into two sets of quads, with eight data converters per quad arranged in IQ pairs as shown in Figs. 3 and 4. Separate clock receivers and bandgap references are provided for each quad and facilitate applica- tion flexibility. For example, having different clock networks 0018-9200 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.