International Journal of Electrical and Electronics Research (IJEER) Open Access | Rapid and quality publishing Research Article | Volume 10, Issue 4 | Pages 1239-1246 | e-ISSN: 2347-470X 1239 Website: www.ijeer.forexjournal.co.in Design of low Power and Process Control Hybrid Adder ░ ABSTRACT- A Hybrid logic style is most popular when compared to other logic styles in implementation of full adder circuits. Conventional hybrid adder uses truth table with true form of carry in and carry out. This will result in non-identical outputs of sum and carry for about 75% of the input combinations. Alternate truth table has been proposed to increase the similarity of sum and carry outputs. In this paper, circuit is designed for complemented carry in and complemented carry out of full adder. This novel structure allowed to design 20-T hybrid adder with process control, low power and low power delay product. The proposed adder structure is applicable for ripple carry adder. The performance of the designs is measured by simulating it in tanner T-spice environment using 0.25um technology. Proposed design has also been implemented up to 64-bit for its scalability. All the results were taken at several operating frequencies with varying word size of the adder. The proposed adder minimizes the power by 9.5%- 51.5% and the power delay product by 3%-60% when compared to its counterparts for N-bit adder. General Terms: Hybrid adder with ripple carry structure for wide word length. Keywords: Adder, Complemented Carry, Process Control, Hybrid logic, Power. ░ 1. INTRODUCTION Electronic system designers aim for low area, low delay and power efficient circuits. Arithmetic circuits are the basic building blocks of many electronic systems. Many of the arithmetic circuits like multipliers uses adders as a basic block [1]. In high-speed microprocessors, 33% of the power is consumed by the arithmetic circuits. To improve the performance of electronic system, adder performance needs to be enhanced [3]. Logic styles can be classified into classical and hybrid logic style. The complementary CMOS is an example of classical approach as in [3]. It gives full swing outputs against supply voltage scaling. Speed of the adder is degraded due to high input capacitance. One more example in classical approach is complementary pass transistor logic as in [3]. This structure offers low delay and full swing outputs. Large number of internal nodes leads to high power consumption. One more classical approach in designing full adders is pass transistors. Pass transistor does not offer full swing at the outputs, when logic “1” is driven through NMOS and logic”0 is driven through PMOS. This issue can be resolved by transmission gate-based approach where the structure has PMOS and NMOS transistors in parallel with their gate inputs connected in true and complemented form. This structure offers weak driving capability and can be resolved by inserting buffers at the intermediate stages. [4] discussed about a system, a low power area reduced and speed improved serial type daisy chain memory register also known as shift Register is proposed by using modified clock generator circuit and SSASPL (Static differential Sense Amplifier based Shared Pulsed Latch). This latch-based shift register consumes low area and low power than other latches. There is a modified complementary pass logic based 4-bit clock pulse generator with low power and low area is proposed that generates small clock pulses with small pulse width. Structure of the full adder is divided into three modules in hybrid design style [5-6]. Full output voltage swing is not produced in XOR/XNOR stage and level restorer is used to achieve it [7]. Hybrid style full adder performance is good as a single unit or for small word lengths. Driving capability is the limitation when word length is more [8]. Hybrid logic style is used for designing the full adders. Pass transistor logic is used for designing XOR-XNOR module in which sum and carry modules are realized using minimal size of a data selector [9]. XOR-XNOR outputs generated simultaneously using pass transistor logic and to design carry output complementary CMOS is used [10]. XOR-XNOR module is generated using feedback transistor, where sum is implemented using pass transistor logic and carry is implemented using minimal size data selector in low power and high-speed adder [11]. Various approaches are presented in recent years for developing XOR- Design of Low Power and Process Control Hybrid Adder with Complemented Carry Structure Bhaskara Rao Doddi 1 , V. Leela Rani 2 and G. Rajita 3 1 Department of Electronics and Communication, GIET University, Gunupur, Odisha, India, bhaskararao.doddi@giet.edu 2 Department of ECE, GVP College of engineering (A), Visakhapatnam, Andhra Pradesh, India, leelarani.vanapalli@gmail.com 3 Department of Electronics and Communication, GIET University, Gunupur, Odisha, India, g.rajita@giet.edu *Correspondence: Bhaskara Rao Doddi; bhaskararao.doddi@giet.edu ARTICLE INFORMATION Author(s): Bhaskara Rao Doddi, V. Leela Rani and G. Rajita; Received: 30/09/2022; Accepted: 14/11/2022; Published: 25/12/2022; e-ISSN: 2347-470X; Paper Id: IJEERSI1205; Citation: 10.37391/IJEER.100475 Webpage-link: www.ijeer.forexjournal.co.in/archive/volume-10/ijeer-100475.html This article belongs to the Special Issue on Applications of Artificial Intelligence and Internet of Things in Process Control Publisher’s Note: FOREX Publication stays neutral with regard to Jurisdictional claims in Published maps and institutional affiliations.