Automatic SystemC TLM Generation for Custom Communication Platforms Lucky Lo Chi Yu Lo Center for Embedded Computer Systems UC Irvine, CA 92697 lochi.yu@uci.edu Samar Abdi Center for Embedded Computer Systems UC Irvine, CA 92697 sabdi@cecs.uci.edu Abstract This paper presents a tool for automatic generation of transaction level models (TLMs) in SystemC for MPSoC de- signs with custom communication platforms. The MPSoC platform is captured as a graphical net-list of components, busses and bridge elements. The application is captured as C processes mapped to the platform components. Once the platform is decided, a set of transaction level commu- nication APIs is automatically generated for each applica- tion C process. After the C code is input, an executable SystemC TLM of the design is automatically generated us- ing our tool. This TLM can be executed using standard SystemC simulators for early functional verification of the design. Although, several TLM styles and standards have been proposed in the past, our approach differs in the fact that the designers do not need to understand the underly- ing SystemC code or TLM modeling style to verify that their application executes on the selected platform. Another key advantage of our tool is that the platform can be easily cus- tomized for the application and a new TLM for that plat- form can be automatically generated. The TLM can be used to program the custom platform early in the design cycle before the components are available. Our experimental re- sults demonstrate that for large industrial applications such as MP3 decoder and H.264, high-speed TLMs can be gen- erated for several platforms in a few seconds. 1 Introduction The rise in complexity, size and heterogeneity of mod- ern embedded system designs has pushed modeling to new abstraction levels above RTL. Transaction level modeling using SystemC is emerging as a new paradigm for sys- tem modeling. On the other hand, platform based design [11] of multi processor SoCs (MPSoC) is being adapted to combine the best features of top down and bottom up sys- tem design. Although several SystemC modeling styles for MPSoC have been proposed, no clear semantics for model- ing objects and composition rules have emerged yet. This makes automatic TLM generation difficult. Most surveys point to usage of transaction level models for early sys- tem verification and embedded SW development. There- fore, SW developers who use TLM have to understand TL modeling and SystemC semantics. In this paper, we pro- pose a system development framework and TLM generation tool that removes the need for SW developers to understand either the platform communication architecture or to learn new modeling languages like SystemC. Figure 1. Design Flow The complete design flow for our tool is shown in Figure 1. The inputs for our tool are the application C code and the platform definition. The output is a TLM from which the software, hardware and interfaces will be synthesized to construct a Pin Cycle Accurate Model to implement in a FPGA or ASIC. This paper will be centered around the TLM generator. The input platform to the generator is a high level net- list of the system consisting of processing elements (PEs), busses and bridges. The bridges interface between busses to allow multi-hop communication. Each PE consists of 1 or more processes that can be accessed on the bus. The pro- cesses themselves are described using a set of C files that contain the functions implemented for that process. The 1-4244-1258-7/07/$25.00 ©2007 IEEE 41