Obstacle-Aware Multiple-Source Rectilinear Steiner Tree with Electromigration and IR-Drop Avoidance Jin-Tai Yan Department of Computer Science and Information Engineering, Chung-Hua University, Hsinchu, Taiwan, R.O.C Zhi-Wei Chen College of Engineering, Chung-Hua University, Hsinchu, Taiwan, R.O.C Abstract—Based on the width determination of any current- driven connection for electromigration and IR-drop avoidance, an area-driven multiple-source routing tree can be firstly constructed to minimize the total wiring area with satisfying the current flow in Kirchhoff’s current laws and the electromigration and IR-drop constraints. Furthermore, some Steiner points can be assigned onto feasible locations to reduce the total wiring area under the electromigration and IR-drop constraints. Finally, an obstacle-aware multiple-source rectilinear Steiner tree can be constructed by assigning the obstacle-aware minimum-length physical paths for all the connections. Compared with Lienig’s multiple-source Steiner tree[7], the experimental results show that our proposed approach without any IR-drop constraint can reduce 10.5% of the total wiring area. Under 10%V dd and 5%V dd IR-drop constraints, the experimental results show that our proposed approach can satisfy 100% electromigration and IR- drop constraints and reduce 7.5% and 4.9% of the original total wiring area on the average for tested examples, respectively. I. INTRODUCTION In general, electronic interconnections in modern integrated circuits have an intended MTTF(mean time to failure) of at least 10 years. The failure of a single interconnection caused by electromigration can result in the failure of the entire circuit. At the end of the 1960s, the physicist J. R. Black developed an empirical model to estimate the MTTF of any interconnection and to take the electromigration factor into consideration[1] as follows: ) exp( T k E J A MTTF a n ⋅ ⋅ = , where A is a material constant based on the cross-sectional area of the interconnection, J is the current density, Ea is the activation energy, k is the Boltzmann constant, T is the temperature and n a scaling factor. The MTTF mainly depends on temperature and current density due to electromigration. Unlike digital circuits, analog circuits must handle a multitude of different current levels, including extremely large currents in some applications. Hence, the interconnection must be designed with the current that will be imposed on it in mind. Interconnect with an insufficient width may be subject to electromigration and eventually might cause the failure of the circuit at any time during its lifetime [1-3]. For analog signal wires, the DC currents where the metal is subject to an electron wind from a constant direction are considered. Because the ongoing reduction of circuit feature sizes has aggravated the electromigration problem, it becomes crucial to address the problems of current densities and electromigration during the routing of the interconnections for analog circuits. Layout for analog circuits has historically been a manual, time-consuming and trial-and-error task. A primary reason for the lack of automation is the vast amount of expert knowledge typically required to meet constraints such as electrical/thermal symmetry, electromigration, voltage drops, temperature gradients, etc. Recently, many current-driven routing approaches[4-9] are proposed to solve the routing problem for electromigration avoidance in analog circuits. For a multiple-source signal net, the routing problem can be divided into wire planning and wire routing. Generally speaking, wire planning determines the routing topology by constructing an area-driven routing tree and wire routing assigns the physical path by constructing an area-driven rectilinear Steiner tree. The proposed approaches discuss different current-driven wire planning techniques and wire routing approaches. For advanced process, the wiring resistance of any signal net dominates the IR-drop result. However, the proposed approaches[4-9] may violate the IR- drop constraint in a multiple-source routing tree during wire planning because of ignoring the effect of the wiring resistances. Besides that, Yan’s approach[8] does not consider the obstacles in a routing plane and Jiang’s approach[9] only considers the wire planning for topology generation. In this paper, based on the width determination of any current-driven connection for electromigration and IR-drop avoidance, an area-driven multiple-source routing tree can be firstly constructed to minimize the total wiring area with satisfying the current flow in Kirchhoff’s current laws and the electromigration and IR-drop constraints. Furthermore, some Steiner points can be assigned onto feasible locations to reduce the total wiring area under the electromigration and IR- drop constraints. Finally, an obstacle-aware multiple-source rectilinear Steiner tree can be constructed by assigning the obstacle-aware minimum-length physical paths for all the connections. II. PRELIMINARIES AND PROBLEM FORMULATION In current-driven analog circuits, the determination of the realistic current value of each terminal in a signal net is important. Most approaches[4-8] use the equivalent current value to model the current value of any terminal in a signal net. 978-3-9810801-7-9/DATE11/©2011 EDAA