A Physical Synthesis Flow for Early Technology Evaluation of Silicon Nanowire based Reconfigurable FETs Shubham Rai 1,3 , Ansh Rupani 1,5 , Dennis Walter 2 , Michael Raitza 1,3 , Andr` e Heinzig 3 , Tim Baldauf 3,4 , Jens Trommer 6 , Christian Mayr 2 , Walter M. Weber 6,3 , Akash Kumar 1,3 (1) Chair For Processor Design, (2) Chair of Highly-Parallel VLSI Systems and Neuro-Microelectronics, (3) CfAED Technische Universit¨ at Dresden, Dresden, Germany (4) HTW-Dresden, Dresden, Germany, (5) BITS Pilani, India, (6) Namlab gGmbH, Dresden, Germany Abstract—Silicon Nanowire (SiNW) based reconfigurable field- effect transistors (RFETs) provide an additional gate terminal called the program gate which gives the freedom of programming p-type or n-type functionality for the same device at runtime. This enables the circuit designers to pack more functionality per computational unit. This saves processing costs as only one device type is required, and no doping and associated lithography steps are needed for this technology. In this paper, we present a complete design flow including both logic and physical synthesis for circuits based on SiNW RFETs. We propose layouts of logic gates, Liberty and LEF (Library Exchange Format) files to enable further research in the domain of these novel, functionally enhanced transistors. We show that in the first of its kind comparison, for these fully symmetrical reconfigurable transistors, the area after placement and routing for SiNW based circuits is 17% more than that of CMOS for MCNC benchmarks. Further, we discuss areas of improvement for obtaining better area results from the SiNW based RFETs from a fabrication and technology point of view. The future use of self-aligned techniques to structure two independent gates within a smaller pitch holds the promise of substantial area reduction. I. I NTRODUCTION Silicon nanowire based functionality enhanced transistors also called reconfigurable transistors (RFETs) provide an alternative path to increase the number of functions offered by a particular logic gate. SiNW RFETs are a potential candidate to complement CMOS technology in selected applications because of their unique polarity control and equalized driving strength for p-type and n-type devices with equal footprint area. Reconfigurability in SiNW RFETs allows the freedom of choosing symmetrical p-type or n-type functionality from the same device as programmed at runtime through a dedicated program voltage. Such polymorphism is generally seen in circuits like FPGAs or CGRAs but at a coarser grain config- uration level. This is also observed in ASICs but it comes at the cost of extra chip area which compensates the gains from scaling. SiNW RFETs offer similar polymorphism at smaller area overheads. Structurally, SiNW RFETs tend to demolish the pull-up and pull-down barrier by combining both of the functionalities. In spite of its great promise, most of the work in this domain has been mainly at the logic level as discussed in [1], [2], [3] and [4]. While [1] demonstrated efficient and exemplary logic gates, [2] and [3] showed the potential of these RFETs in bigger circuits and SOC core components respectively. DeMarchi et al. in [5] explained device characterization for SiNW RFETs. Further, they provided a detailed explanation of device fabrication using a stacked nanowire approach. They also showed that XOR logic is an inherent function of the device itself. On the other hand, [6] demonstrated a novel layout technique to address the routing congestion arising from the extra gate terminal in the SiNW RFET. However, their approach was technology independent and they showed layouts for basic logic gates only. None of these works has tried to demystify the entire design flow – logic synthesis up to physical synthesis for SiNW RFETs. Neither is there an evaluation of silicon nanowires through a parallel CMOS standard flow from a technology per- spective. We have not considered vertically stacked nanowire FETs as mentioned in [5]. We have formalized a complete physical synthesis flow along with layouts for various logic gates. Then, using these logic gates, we ran the entire flow and compared area numbers for MCNC benchmark [19] circuits with the standard CMOS flow. We define both static and reconfigurable ready layouts of logic gates. For simplicity, we have exclusively used dual gate RFETs as our basic building blocks. Contributions: Major contributions of the present work are– • Based on the electrical characterization of SiNW RFETs, a table model was proposed based on the I-V properties of scaled silicon nanowire ribbons considering stressors to adjust symmetry [7]. We propose a 22 nm technology to pattern the minimal individual nanowire ribbon width and to define the half pitch between parallel arranged nanowire channels. The target technology in our paper is the fully symmetrical RFET as proposed in [8], adapted to an SOI platform. • We propose for the first time the layouts for a set of logic gates based on SiNW RFETs. We also extend these layouts to demonstrate a reconfigurable ready layout for the MINORITY logic gate. • We provide a physical synthesis flow along with a stan- dard cell library under an open source license including LEF and Liberty files to facilitate further research from the technology point of view [9]. We studied various aspects by running the above flow with MCNC benchmarks to get the area numbers for SiNW based circuits and compared them to the standard CMOS flow. A detailed analysis in order to achieve better area numbers has been done from the manufacturing and fabrication point of view. This has been done to promote SiNW as a technology that can be co-integrated with CMOS, e.g. for selected applica- tions employing inherent reconfigurability, such as hardware security circuits [10]. The present work has been organised in the following sections. Section II explains about silicon nanowire as technology and how its transfer characteristics have been used to formalize the layout and generate the LEF and Liberty files. Section III summarizes the experimental setup and provides a detailed analysis of the results of our experiments. This is followed by concluding remarks in Sec- tion IV. 605 978-3-9819263-0-9/DATE18/ c 2018 EDAA