APPLIED PHYSICS REVIEWS—FOCUSED REVIEW Frontiers of silicon-on-insulator G. K. Celler a) Soitec USA, 2 Centennial Drive, Peabody, Massachusetts 01960 Sorin Cristoloveanu Institute of Microelectronics, Electromagnetism and Photonics (UMR CNRS, INPG & UJF), ENSERG, BP 257, 38016 Grenoble Cedex 1, France Received 18 September 2002; accepted 10 December 2002 Silicon-on-insulator SOI wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. After more than three decades of materials research and device studies, SOI wafers have entered into the mainstream of semiconductor electronics. SOI technology offers significant advantages in design, fabrication, and performance of many semiconductor circuits. It also improves prospects for extending Si devices into the nanometer region 10 nm channel length. In this article, we discuss methods of forming SOI wafers, their physical properties, and the latest improvements in controlling the structure parameters. We also describe devices that take advantage of SOI, and consider their electrical characteristics. © 2003 American Institute of Physics. DOI: 10.1063/1.1558223 TABLE OF CONTENTS I. INTRODUCTION............................ 4956 A. Motivation to develop SOI................. 4956 B. Comments on bibliography................. 5958 II. FABRICATION METHODS................... 4959 A. Brief overview........................... 4959 B. SIMOX process.......................... 4959 1. Early developments and ‘‘standard dose’’ implants.............................. 4959 2. Thinner buried oxide and internal oxidation............................. 4960 3. Patterned buried oxide.................. 4960 C. Processes based on wafer bonding........... 4960 1. Bonding mechanism.................... 4960 2. Bonding and Etchback: BESOI........... 4962 3. Hydrogen implantation: Smart Cut™ process.............................. 4962 a. Discovery of controlled exfoliation..... 4962 b. Process description.................. 4963 c. Hydrogen splitting/separation mechanism......................... 4964 4. Variations on wafer bonding and hydrogen-related splitting................ 4965 a. Hydrogen and helium................ 4965 b. Hydrogen and boron................. 4965 c. Hydrogen at heteroepitaxial interface.... 4965 d. Strained Si on insulator SSOI........ 4965 5. Porous Si based process: ELTRAN........ 4966 III. CHARACTERIZATION OF SOI WAFERS...... 4966 A. Si and BOX thickness measurements......... 4967 B. Structural defects......................... 4968 C. Electrical characterization of SOI material..... 4968 1. Pseudo-MOSFET...................... 4968 2. Other measurements.................... 4968 3. Device-based characterization............ 4969 IV. SOI DEVICES............................. 4969 A. Motivations for SOI circuits................ 4969 B. CMOS/SOI circuits....................... 4970 C. Bipolar and high-voltage SOI devices......... 4970 V. TYPICAL MECHANISMS IN SOI TRANSISTORS............................. 4971 A. Fully depleted MOSFETs................... 4971 B. Partially depleted MOSFETs................ 4071 VI. NEW DIRECTIONS IN SOI DEVICES........ 4972 A. Short-channel effects SCE................. 4972 B. Scaling trends............................ 4973 C. Ultimately small MOSFETs................. 4974 D. Double-gate MOSFETs.................... 4974 E. From microelectronic to nanoelectronic devices................................. 4975 1. Four-gate transistor..................... 4975 2. Tunneling devices...................... 4975 3. Single-electron transistors............... 4975 VII. CONCLUSIONS........................... 4975 ACKNOWLEDGMENTS....................... 4976 REFERENCES............................... 4976 a Electronic mail: gceller@soitecusa.com JOURNAL OF APPLIED PHYSICS VOLUME 93, NUMBER 9 1 MAY 2003 4955 0021-8979/2003/93(9)/4955/24/$20.00 © 2003 American Institute of Physics Downloaded 30 May 2003 to 131.243.19.74. Redistribution subject to AIP license or copyright, see http://ojps.aip.org/japo/japcr.jsp