874 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL 39, NO zyxw 4, APRIL 1992 Detailed Analysis of Edge Effects in SIMOX-MOS Transistors Tarek Elewa, Bendik Kleveland, Sorin Cristoloveanu, Boubaker Boukriss, and Alain Chovet Abstract-A comprehensive investigation of edge effects in LOCOS-isolated silicon on insulator devices is made by com- bining the measurements of the static characteristics, charge pumping, and noise. Even when a substrate bias is used to mask the conduction on the island edges, the high-frequency edge effects are still detectable. Appropriate models are proposed to separate the edge contribution from those of the front and back interfaces. It is found that the defect density on the edges is inhomogeneous, increasing vertically from the top to the bot- tom of the film and laterally from the middle zyxwvutsrq to the end of the channel. Slow traps are identified at the back interface, close to the sourceldrain junctions. I. INTRODUCTION HE DEVICE isolation technology has received con- T siderable attention in bulk Si. The bird’s beak for- mation and the edge doping encroachment for LOCOS isolation are increasingly limiting factors for small-ge- ometry devices and new isolation alternatives are under test zyxwvutsrqpo [ 11, [2]. Silicon on insulator (SOI) materials, which offer a natural isolation between devices, have experi- enced a unprecedented development in recent years [3]. Although a low-temperature MESA isolation can be eas- ily achieved and the LOCOS bird’s beak formation is re- duced for very-thin SO1 films, the edge effects are not eliminated [4]. Both MESA and LOCOS isolations result in subthreshold leakage between source and drain and high off-state currents due to a lower value zyxwvuts of the threshold voltage on the Si island edges. The conventional method of masking this parasitic conduction is to increase its threshold voltage by heavily implanting the edges. How- ever, the channel doping of state-of-the-art submicrome- ter transistors is already very high so that the necessary additional edge doping becomes prohibitive. On the other hand, an increase of the gate oxide thickness of the edges, as is the case for the combination of MESA and LOCOS zyxwvu [5], can also reduce edge conduction. The drawback is Manuscript received October 5, 1990; revised May zyxwvutsrqp 14, 1991. This work was partially funded by Esprit, JESSI, and GCIS projects. The review of this paper was arranged by Associate Editor A. F. Tasch, Jr. T. Elewa, S. Cristoloveanu, B. Boukriss, and A. Chovet are with La- boratoire de Physique des Composants Semiconducteurs (UA-CNRS), Institut National Polytechnique, ENSERG, BP 257, 38016 Grenoble Cedex, France. B. Kleveland was with the Laboratoire de Physique des Composants a Semiconducteurs (UA-CNRS), Institut National Polytechnique, ENSERG, BP 257, 38016 Grenoble Cedex, France. He is now with Intel Corporation, M/S ST6-69, Santa Clara, CA 95052. IEEE Log Number 9105908. that the specific rad-hard SO1 applications are affected be- cause the amount of radiation-induced defects increases with oxide thickness. It is known that SO1 has major ad- vantages over bulk Si, but the edge effects represent a critical obstacle preventing the full achievement of the ex- pected circuit performances. The study and optimization of the edges stands as an important issue in the future of both SO1 and bulk Si devices. The conventional method of evaluating the efficiency of edge doping or other isolation solutions is based on threshold voltage and subthreshold current measure- ments. In this paper, we will demonstrate interest in a more thorough investigation using complementary inter- face characterization techniques. It will be shown that the properties of the LOCOS edges in SIMOX transistors can be determined by combining the information delivered by the static characteristics, charge pumping, and noise mea- surements. 11. STATIC CHARACTERISTICS The SIMOX wafers were fabricated by deep oxygen implantation (dose 1.8 X 10l8 cm-’, current zyxw 55 PA, en- ergy 200 keV, temperature 550°C) and annealing at 1300°C for 5 h in nitrogen ambient. LOCOS oxides were used to isolate the Si islands (Fig. ](a)). After the pro- cessing of n-channel enhancement-mode MOSFET’s the thicknesses of the gate oxide, buried oxide, and Si film were 28, 400, and 300 nm, respectively. As the channel doping was NA = cm-j, the Si film was not fully depleted. The transistors under inspection had different dimensions and geometries (i.e., with edges and edge- less). The front and back-channel static Id( VRf,J character- istics of several different transistors have been measured with an HP-4 145 Semiconductor Parameter Analyzer and are compared in Fig. 1. Two curves in Fig. l(b) exhibit a double slope in the subthreshold region. The first slope, which shows up for negative values of the front gate volt- age Vgf, is obviously due to a parasitic current definitely flowing on the transistor sidewalls and not at the back in- terface. This is confirmed by the fact that transistors with the same length L and different widths W show identical characteristics in the initial subthreshold region, the wider transistor driving more current only for Vgf > 0.5 V. Moreover, the edgeless transistor does not suffer from this parasitic component and presents a single slope. 0018-9383/92$03.00 zyxwvuts 0 1992 IEEE