I.J. Information Engineering and Electronic Business, 2012, 4, 39-45 Published Online August 2012 in MECS (http://www.mecs-press.org/) DOI: 10.5815/ijieeb.2012.04.06 Copyright © 2012 MECS I.J. Information Engineering and Electronic Business, 2012, 4, 39-45 Memetic Programming Approach for Floorplanning Applications Dr. R. Varatharajan, Department of ECE S.M.K Fomra inst. Of tech Chennai. varathu21@yahoo.com Muthu Senthil Department of CSE S.M.K Fomra inst.tech Chennai. bmssen@gmail.com Dr. Perumal sankar Research Director Cape Institute of Tech Kanyakumari spsankar2004@yahoo.com Abstract — Floorplanning is a very crucial step in modern VLSI design. It dominates the top level spatial structure of a chip and initially optimizes the interconnections. Thus a good floorplan solution among circuit modules definitely has a positive impact on the placement, Routing and even manufacturing. In this paper the classical floorplanning that usually handles only block packing to minimize silicon rate, so modern floorplanning could be formulated as a fixed outline floorplanning. It uses some algorithms such as B-TREE representation, simulated annealing and adaptive fast simulated annealing, comparing above three algorithms the better efficient solution came from adaptive fast simulated annealing, it’s leads to faster and more stable convergence to the desired floorplan solutions, but the results are not an optimal solution, to get an optimal solution it’s necessary to choose effective algorithm. Combining global and local search is a strategy used by many optimization approaches. Memetic algorithm is an evolutionary algorithm that includes one or more local search phases within its evolutionary cycle. The algorithm combines a hierarchical design technique, genetic algorithms, constructive techniques and advanced local search to solve VLSI floorplanning problem. Index terms — Floorplan problem, memetic algorithm, local search, area, delay, layout optimization I. INTRODUCTION Floorplanning has become a very crucial step in modern very large scale integration (VLSI) designs. As the start of physical design flow, floorplanning not only determines the top-level spatial structure of a chip, but also initially optimizes the interconnections. Thus, a good floorplan solution among circuit modules definitely has a positive impact on the placement, routing, and even manufacturing. In the nanometer scale era, the ever-increasing complexity of integrated circuits (ICs) promotes the prevalence of hierarchical design. However, as pointed out by Kahng [1] , classical outline-free floorplanning [2] cannot satisfy such requirements of modern designs. In contrast with this, fixed-outline floorplanning enabling the hierarchical framework is preferred by modern application specific integrated circuit designs. Nevertheless, fixed-outline floorplanning has been shown to be much more difficult, compared with classical outline-free floorplanning, even without considering wirelength optimization [7]. A common strategy for blocks floorplanning is to determine in the first phase and then the relative location of the blocks to each other based on connection-cost criteria. In the second step, block sizing is performed with the goal of minimizing the overall chip area and the location of each block is finalized [1] . Simulated annealing (SA) has been considered a good tool for complex nonlinear optimization problems. The technique has been widely