IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 11, NOVEMBER 2014 3175 A Low Energy and High Performance Adder Itamar Levi, Amir Albeck, Alexander Fish, Member, IEEE, and Shmuel Wimer, Member, IEEE Abstract—A novel Dual Mode Square adder is pro- posed. The adder achieves low energy, high performance and small area by combining two independent techniques recently proposed by the authors: dual-mode logic (DML) and dual-mode addition (DMADD). DML is a special gate topology that allows on-the-fly adaptation of the gates to real time system requirements, and also shows a wide energy-performance tradeoff. DMADD is probability based circuit architecture with a wide energy-perfor- mance tradeoff; however its utilization in a pipelined processor requires multi-cycle operation in some cases. We show how DML circuits avoid this requirement, and thus make it possible to transparently plug-in the adder and derive full benefits from the DMADD. Previous work showed that the DMADD can lead to energy savings of up to 50% at the same clock cycle, com- pared to conventional CMOS solutions. Simulation results in a 40 nm standard process shows that the proposed approach achieves additional energy savings of 27% to 36% for 64-bit and 32-bit adders, respectively, compared to DMADD. Index Terms—Adders, DML, low-power design. I. INTRODUCTION O BTAINING energy efficiency and low peak power while maintaining computational performance is one of the primary goals in contemporary processor design. Energy reduction and performance improvement have been studied extensively from the very high level of application algorithms, through system [1], architecture [2], [19] and logic levels, to the gate [3]–[7], [19], circuit, device and interconnect levels [8], [9]. Energy reduction in the context of pipelined digital systems has also been studied in [19] and [20]. For example, approaches such as circuit sizing and supply voltage scaling have been utilized and analyzed [19]. This work combines recently proposed gate and architecture levels approaches. It shows how the combination of two inde- pendent methods yields considerable performance enhancement and energy efficiency. The first method is dual-mode addition (DMADD) [10]. It takes advantage of the carry probability to perform low-power addition and leading to a considerable energy reduction of up to 50% compared to conventional designs. However, it requires some pipeline modifications to support multi-cycle addition. The second method is a logic gate topology called dual-mode Manuscript received December 24, 2013; revised May 12, 2014 and June 10, 2014; accepted June 18, 2014. Date of publication July 17, 2014; date of current version October 24, 2014. This work was supported by the Israel Sci- ence Foundation (ISF Grant) under Grant Number 1678/13. Dual Mode Logic methodology was developed in the frame of the Kamin Grant of the Office of the Chief Scientist (OCS) in the Ministry of Economy. This paper was recom- mended by Associate Editor M. Seok. The authors are with the Bar-Ilan University, Ramat Gan 52900, Is- rael (e-mail: itamarlevi@gmail.com; amiralbeck@gmail.com; shmuel. wimer@biu.ac.il; alexander.fish@gmail.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSI.2014.2334793 logic (DML) comprising static and dynamic operation modes within the same gate [11]–[14], In this paper we propose Squared Dual Mode ap- proach combining DMADD and DML. main objective is to eliminate the DMADD need for multi-cycle addition by re- placing its ordinary CMOS logic with DML, thus avoiding the architectural overheads. Furthermore, enables consider- able energy savings due to the inherent properties of the DML gates. Two adders were implemented using the method in a standard 40 nm process. Theoretical analysis and post-layout simulations prove the efficiency of exhibiting energy saving of up to 36%, as compared to the DMADD. The rest of this paper is organized as follows: Section II briefly presents DMADD and DML techniques. Section III describes the DMADD and DML integration into the , including a theoretical analysis and circuit design optimization. Simulations of 40 nm adders and their comparison to standard CMOS based DMADD, Brent-Kung and Ripple adders are presented in Section IV. Section V concludes the paper. II. DML AND DMADD OVERVIEW A. DMADD DMADD comprises two addition modes [10]. The energy ef- ficient one-cycle mode, called normal, is used most of the time to properly compute addition. It takes advantage of the average (expected) longest carry in addition which is , and is much shorter than the adder size . The probability of -bit carry propagation is nearly zero [17]. The second mode, called extended, occurs very infrequently and requires several clock cycles to properly add. The decision of which mode should take place requires an appropriate control circuit. When this control is used in a pipelined processor it selects the proper mode at the instruction decode (ID) stage, prior to the ALU stage. The probability of a carry to propagate through a bit is (1/2) and the propagation probability through successive bits is therefore . The probability that it takes exactly bits for a carry to either be generated or killed is: (1) where is the propagate signal of bit . It was shown in [10] that adders designed for -bit carry propagation yields considerable energy efficiency compared to ordinary -bit carry propagation designs. An -bit DMADD comprises groups of bits each, where, , such that the carry propagation delay of two -bit adders meets the clock cycle. It enables a few design alterna- tives to reduce energy. A design for a -bit delay rather 1549-8328 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.