1122 A 1V Buck Converter IC with Hybrid Current-Mode Control and a Charge-Pump DAC Olivier Trescases *, Nabeel Rahman *, Aleksandar Prodi´ c, Wai Tung Ng University of Toronto, Department of Electrical and Computer Engineering 10 King’s College Road, Toronto, ON, M5S 3G4, Canada Abstract— This paper presents an integrated dc-dc converter with an output voltage of 1 V for portable applications. A hybrid peak current-mode control-scheme is demonstrated, where the voltage-loop compensation is achieved in the digital domain, while the current-regulation loop has a more traditional analog implementation. The main contribution of this work is the novel DAC architecture, which was developed specifically to achieve fast transient-response without needing clock frequencies beyond fs, or expensive signal processing. Unlike the previous approach, based on an adaptive ΔΣ DAC, the charge-pump (CP) DAC is capable of rapidly increasing the current-command in a single- cycle during load-steps. In addition to a low steady-state current- consumption of 3 μA, the CP-DAC has a guaranteed monotonic transfer characteristic and simplifies the overall system architec- ture. The resulting system solution achieves dynamic response comparable to state-of-the-art analog current-mode solutions, without using a power-hungry controller, or quantizing the inductor current. A custom IC, which was fabricated in a 0.18 μm CMOS process with 5 V compatible transistors, achieves a response-time of 4 μs at fs = 3 MHz and Vout = 1 V, for a 200 mA load-step. The active area of the controller is only 0.077 mm 2 , and the total controller current-draw, which is heavily dominated by the on-chip senseFET current-sensor, is below 0.5 % of the load current at Iout= 50 mA. I. I NTRODUCTION Peak current-mode control (CPM) provides inherent cycle- by-cycle current-limiting and simplified loop dynamics, which allows simple and robust compensation of the control-loop. Previous work [1], [2] has reported a mixed-signal, or hy- brid current-mode scheme for low-power (sub 1-W) dc-dc converters, where voltage-loop compensation is carried out in the digital domain, while the current-regulation loop has a traditional analog implementation. Using this configuration, a DAC is required at the interface of the two loops, in order to generate an analog current command. This approach results in flexible digital compensation without the need for sampling the inductor current, and also without requiring a high-frequency digital pulse-width modulator, unlike fully digital techniques [3]–[5]. In [2], a noise-shaping (ΔΣ) DAC was used to meet the stringent resolution requirements, but it was shown that the low-pass reconstruction filter in the DAC introduces an unde- sirable pole in the system transfer function. This pole limits the control bandwidth and overall regulation performance. An adaptive control scheme was developed to address this issue [2], where the DAC over-sampling rate and filter corner * Olivier Trescases is currently with the High-Integration Group in the Automotive Power Department, Infineon Technologies AG Siemenstrasse 2, Villach, A9500, Austria. Nabeel Rahman is currently working for On Semiconductor 5005 E.Mcdowell Road, Pheonix, AZ, USA. frequency are varied in real-time to achieve both low steady- state power consumption and fast transient response. In this work, a simple low-power DAC architecture was applied to the hybrid scheme for a synchronous buck converter IC, as shown in Fig. 1. The IC includes the control circuits, as well as a segmented power-stage [6] for improving light-load efficiency. In this work, the aim is to eliminate the main shortcomings of the previous ΔΣ DAC approach, namely the bandwidth restriction imposed by the DAC’s low-pass filter, while at the same time generating a high resolution voltage reference for the current-loop. In addition, the demonstrated architecture does not require expensive digital signal processing or high- frequency clocks beyond the switching frequency, f s .                                                                           Fig. 1. Simplified architecture of the integrated dc-dc converter with a hybrid CPM control scheme and the novel DAC. This paper is organized as follows. The limit-cycle phe- nomenon, which may occur in hybrid peak current-mode control, is examined in Section II, leading to minimum res- olution requirements on the DAC. The proposed low-power DAC architecture for linking the voltage and current loops is presented in Section III and experimental results for the silicon prototype are reported in Section IV. II. MINIMUM DAC RESOLUTION: DC LIMIT-CYCLE CONDITION The two quantizers (the DAC and the ADC) in the feedback loop make hybrid CPM prone to limit-cycle oscillations, a phenomenon which is well understood in digital voltage- mode controllers [7], [8]. In this Section, the analysis method presented in [7] is extended for the hybrid CPM. The DC output voltage change caused by changing the DAC input by one LSB, ΔV dac , is given by ΔV dac = G vc (s = 0) K s · V r 2 M = G vc0 K s · V r 2 M (1) 978-1-4244-1668-4/08/$25.00 ©2008 IEEE