RESEARCH ARTICLE Fast adaptive comparator offset calibration in pipeline ADC with self‐repairing thermometer to binary encoder Antonio José Ginés | Eduardo José Peralías | Cristina Aledo | Adoración Rueda Instituto de Microelectrónica de Sevilla, IMSE‐CNM, (CSIC, Universidad de Sevilla), Seville, Spain Correspondence Antonio José Ginés, Instituto de Microelectrónica de Sevilla, IMSE‐CNM, (CSIC, Universidad de Sevilla), Seville 41092, Spain. Email: gines@imse‐cnm.csic.es Funding information European FEDER program; Spanish Government projects, Grant/Award Number: TEC2011‐28302 and TEC2015‐ 68448‐R Summary This paper presents a fast background calibration method for comparator offsets in pipeline ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC with 15‐bit resolution (74 dB‐Signal‐to‐noise plus Distortion Ratio [SNDR]). A self‐repairing (SR) thermometer‐to‐binary encoder is developed to deal with malfunctioning in presence of high compar- ator offsets greater than one‐half least‐significant bit (LSB). In this situation, the effective thresholds between two adjacent comparators could be inverted leading to a faulty behavior with conventional architectures. The proposed solution allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed. As demonstrator, its applica- tion to a 15‐bit pipeline ADC using a novel calibrated dynamic‐latch compara- tor (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration targeting the same specifications. KEYWORDS pipeline ADCs, comparator offset, background calibration, dynamic‐latch comparators 1 | INTRODUCTION Coarse quantization of the analog signals in pipeline ADCs is carried out by the subADCs along the stage queue. These subconverters use the flash structure and basically rely on dynamic‐latch comparators (DLCs) to achieve high speed operation. Positive feedback within DLCs 1,2 minimizes the decision time for a given power and area consumption, thereby improving the ADC through output. Unluckily, DLCs with no resistor ladder and no preamplifier 3,4 are prone to errors due to device and parasitic impairments, 5 showing offset values as big as 0.2 V. Although existing digital correction in pipeline ADCs provides an offset safety margin of one‐half least‐significant bit (LSB), 6 its application is practically limited to 1.5‐bit stages. 7 The uses of DLCs in stages with more resolution typically implies solutions based on analog calibration, 8-10 extra operation phases for offset estimation/compensation, 11,12 or front‐end preamplification, trading‐off comparator accuracy, power consumption, conversion frequency, and input impedance. This trade‐off has a negative effect on design specifications of the operational amplifier (op‐amp) in each stage doing the residue generation, since its driving capability and output swing (OS) are highly dependent on the input impedance and offset of comparators. An alternative for overcoming comparator offset in flash ADCs is digital calibration. 13-17 In foreground tech- niques, 13,14 calibration is performed just after power on, and therefore, any error due to temperature variations, polar- ization changes, or component aging requires interrupting conversion to start a new recalibration cycle. Background Received: 6 September 2018 Revised: 20 December 2018 Accepted: 21 December 2018 DOI: 10.1002/cta.2594 Int J Circ Theor Appl. 2019;1–17. © 2019 John Wiley & Sons, Ltd. wileyonlinelibrary.com/journal/cta 1