Nguyen, Adams and Sweetland: zyxwvutsrqpo A 113dB SNR Oversampling Sigma-Delta DAC for CD/DVD Application zyxwv 1019 Digit$ Interpolation EA input filter - modulator - zyx A 11 3dB SNR OVERSAMPLING SIGMA-DELTA DAC FOR CD/DVD APPLICATION Khiem Nguyen, Robert Adams and Karl Sweetland Analog Devices Inc., Wilmington, MA USA Switched-cap Analog filter dutput zyxwvutsrq Abstruct- A sigma-delta (CA) audio digital-to-analog converter (DAC) for CD and digital versatile disk (DVD) application is presented. The converter uses a 6-bit mod- ulator and a segmented noise-shaped scrambling tech- nique to achieve a 113dB dynamic-range over a 20kHz bandwidth. A continuous-time output stage is used to achieve high signal-to-noise (SNR) in a small die area. This output stage employs a dual return-to-zero scheme to eliminate errors caused by inter-symbol interference (ISI). The converter is fabricated in a 0.6pm double-poly double-metal CMOS process. The chip occupies 3.1x3.2 squared mm and operates from a single 5V supply. I. INTRODUCTION Sigma-delta (CA) digital-to-analog converters (DACs) offer a way to achieve high resolution and low distortion with relaxed post-analog filter requirements at a relatively low cost compared to conventional Nyquist converters. A typical EA DAC as in Fig. 1 consists of a digital interpolation filter to bring the input sample rate up to the modulator rate, a modulator to reduce the word width by trading off the out-of- band noise, a switched-capacitor filter for out-of-band noise filtering and analog signal reconstruction. To achieve perfect linearity in analog signal reconstruction, the modulator out- put is usually 1-bit, This type of architecture has several drawbacks. Modulators with 1-bit quantizers create large step sizes at the discrete-to-continuous boundary and hence require a tight clock jitter specification. For example, to achieve +100dB SNR over the audio band, it would need a master clock with jitter of less than lops. One approach to reduce the clock jitter sensitivity is to use a multi-bit quan- tizer. Multi-bit DACs’ suffer from distortion problem caused by the analog element mismatch. Techniques such as those presented in [1] or [2] can be used to dynamically swap the elements so that on average the mismatch error is zero. One drawback is that the swapping circuitry becomes large when the word width is greater than four. Fig. 1 Block diagram of a typical CA DAC The major disadvantage of EA DACs with switched- capacitor filters is the relationship between the noise power and the capacitor area. The noise power each capacitor accu- mulates is described by the equation zyxw P, = zyxw kT/ C . It follows that each additional bit of resolution increases the capacitor area by four times. Since the capacitors are larger, they will need higher slew rate, faster on-chip opamps, and larger switches for settling to the desired accuracy. These require- ments make the design very expensive. This paper presents a multi-bit EA DAC with a continu- ous-time output stage. The continuous-time output stage enables the design to achieve high SNR while occupying much less area than normal switched-capacitor circuits. To reduce the out-of-band noise energy, a multi-bit modulator is used. A new noise-shaped segmentation technique is used in conjunction with scrambling to achieve low distortion at a very small hardware cost. The output stage uses a dual return-to-zero switching scheme which yields an output cur- rent pulse that is free of inter-symbol interference. High per- formance on-chip opamps are used for I-to-V conversion. The chip architecture and design will be discussed in section 11. Section I11 will discuss about the circuit design issues. Section IV will show some of the measured results. 11. ARCHITECTURE Fig. 2 shows the block diagram of one DAC channel. The chip consists of a serial port to receive the 3-wire input, a selectable 4xBx interpolator, a 16x sample-and-hold register, a second-order 6-bit modulator operating at 128f,, and a con- tinuous-time output stage. The selectable interpolation factor allows the input sample rate to be either 44.lkHz or 88.2kHz. The digital filter engine also includes a digital volume con- trol circuit and an IIR filter that performs the required de- emphasis filtering found in some CDs. The continuous-time output stage is used since its output noise power is domi- nated by the thermal noise of the MOS current sources which can be optimized. Hence, a high SNR design can be achieved in a smaller area compared to that of a switched capacitor fil- ter output stage. A. Multi-bitmodulator For single-bit ZA DACs, the sample-to-sample step size at the discrete-to-continuous time boundary will swing from rail to rail. Hence, the output waveform is very sensitive to clock jitter. In addition, the continuous-time output stage relies on the external analog filter to remove the out-of-band Manuscript received June 8, 1998 0098 3063/98 $10.00 1998 IEEE