378 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 11, NO. 3, SEPTEMBER 2011 Physically Based Modeling of Stress-Induced Variation in Nanoscale Transistor Performance Nuo Xu, Student Member, IEEE, Lynn Tao-Ning Wang, Member, IEEE, Andrew R. Neureuther, Fellow, IEEE, and Tsu-Jae King Liu, Fellow, IEEE Abstract—Uniaxial stress is widely used in advanced CMOS technologies to boost transistor performance. Conventional com- pact transistor models rely on empirical fitting of the average channel stress value to predict mobility and, hence, transistor per- formance. This approach can lead to significant errors for deeply scaled technologies. In this paper, stress profiles are modeled in an- alytical form, using a physically based approach. The stress model is validated by 3-D TCAD simulations. A nanometer-scale tran- sistor intrinsic delay formula based on injection velocity theory is then applied. The predicted variation in transistor performance compares well with the measured silicon data for a 45-nm strained CMOS technology. Index Terms—Analytical model, injection velocity, layout- dependent variation, mobility, stress. I. I NTRODUCTION U NIAXIAL STRESS was introduced at the 90-nm CMOS technology node to boost transistor performance [1]. Typically, a highly stressed contact etch-stop liner (CESL) capping layer is used to induce stress in the channel region and thereby enhance the field-effect mobility. Tensile CESL is used to enhance electron mobility in n-channel MOSFETs, while compressive CESL is used to enhance hole mobility in p-channel MOSFETs. CESL-induced stress is not uniform throughout the channel region, however, so the degree of cur- rent enhancement is layout dependent, resulting in systematic variation in transistor performance. At the 45-nm CMOS tech- nology node, CESL-stress-induced circuit performance varia- tion dominates lithography- and etch-induced variations [2]. Hence, a transistor-level model or simulation methodology to capture stress-induced systematic variation is needed for variation-aware IC design. Presently, there are two established methods for assessing the impact of process-induced stress variation on transistor performance. The first method is TCAD simulation, which uses the finite-element method to approximate the exact solu- tion of force and displacement equations numerically at each Manuscript received November 3, 2010; revised February 11, 2011; accepted April 5, 2011. Date of publication April 21, 2011; date of current version September 2, 2011. This work was supported by UC Discovery Grant ele07- 10283 under the IMPACT Program. N. Xu, A. R. Neureuther, and T.-J. K. Liu are with the Department of Elec- trical Engineering and Computer Sciences, University of California–Berkeley, Berkeley, CA 94720-1770 USA (e-mail: nuoxu@eecs.berkeley.edu). L. T.-N. Wang was with the University of California–Berkeley, Berkeley, CA 94720 USA. She is now with GLOBALFOUNDRIES, Milpitas, CA 95035 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TDMR.2011.2144598 Fig. 1. (a) Schematic cross section of a nanoscale MOSFET with tensile CESL. (b) Layout of a 45-nm CMOS RO. mesh point. This method is computationally intensive, so large- scale layout simulation is prohibitively expensive. The second method is compact modeling using average channel stress values obtained empirically with specific layout geometries [3], [4]. This method can result in inaccurate performance predictions since it is not physically based. Carrier transport in scaled MOSFETs is highly localized, varying with position [5]. For a very short channel length, the carrier velocity in the channel at the location corresponding to the peak of the source- side potential barrier determines the MOSFET ON-state current [5]. This phenomenon is referred to as the “injection velocity limit.” The transistor drive current is affected by the velocity within a critical length (l) of the source-potential peak, shown in Fig. 1(a). Thus, the value of effective channel stress that should be used to determine the transistor performance parame- ters is the average stress value within this critical-length region. Tracking of transistor performance variation by measuring ring oscillator (RO) frequencies has been shown to be an efficient method to make large-scale measurements using only a few input/output pads [6]. The evaluation of RO frequencies for different inverter layouts helped to identify causes of layout- dependent circuit performance variability in 90- and 45-nm CMOS circuits [2], [7]. The RO array developed in [2] uses a 13-stage RO and control logic circuit as a unit cell, and it is used to provide experimental data for studying layout-dependent variation. The length of the source/drain (S/D) (“diffusion”) re- gions (LOD) is varied in several instances to provide different channel stress values. In this paper, a new analytical approach to calculate channel stress profiles is first presented and validated by 3-D TCAD simulations for different layout configurations. The TCAD tool used in this work is the Sentaurus suite [8], which is cali- brated with up-to-date experimental results for semiconductor mechanical parameters [9]. Then, an advanced device perfor- mance model based on the injection velocity limit is developed. Finally, the transistor performance variation predicted using 1530-4388/$26.00 © 2011 IEEE