A 1.55 GHz to 2.45 GHz Center Frequency Continuous-Time Bandpass Delta-Sigma Modulator for Frequency Agile Transmitters Martin Schmidt, Markus Grözing, Stefan Heck, Ingo Dettmann, Manfred Berroth Institute of Electrical and Optical Communications Engineering University of Stuttgart, Stuttgart, Germany Dirk Wiegner, Wolfgang Templ, Andreas Pascht Alcatel-Lucent Bell Labs Stuttgart Stuttgart, Germany Abstract—This paper presents a 4 th order continuous-time bandpass delta-sigma modulator (CT-BPDSM) with a programmable center frequency ranging from 1.55 GHz to 2.45 GHz. The modulator is suited to be applied in multi- standard class-S power amplifiers. The circuit features a multi-feedback architecture with return-to-zero (RZ) and half-return-to-zero (HRZ) pulses. The loop filters consist of LC-resonators with emitter degenerated input transconductors and Q-enhancement circuits. A configuration register allows to program the resonator input transconductors, the Q-enhancement circuits and the resonator capacitances with 5 bit resolution. Fine tuning of the resonator center frequency is achieved with varactors. The circuit is implemented in a 200 GHz-f T SiGe-bipolar technology. The measured SNR at 2.2 GHz center frequency is 45.5 dB in a bandwidth of 20 MHz. At 1.55 GHz the SNR decreases to 40.7 dB. The measured uplink UMTS-FDD ACLR (adjacent channel leakage power ratio) of the modulator output is 48.4 dB in the first adjacent channel. Index Terms — Delta-sigma modulator, class-S power amplifier, bipolar integrated circuit. I. INTRODUCTION The strong growth of mobile communications has led to many different standards. Users expect their mobile terminals to work in any environment and at different locations, whereas operators want to minimize their hardware effort by reconfigurable or programmable base station equipment. As a result, mobile terminals as well as base stations should provide access to several coexisting standards in different frequency bands. The coding schemes in recent standards like UMTS (Universal Mobile Telecommunications System) exhibit higher peak to average power ratios (PAPR) than older ones like GSM (Global System for Mobile communications). This turns out to be a severe problem for the power amplifier (PA) in the transmission chain: The higher the PAPR the higher the back-off a conventional linear PA has to provide and thus the lower the power efficiency will be. The multitude of coexisting standards and the PA power efficiency are two of the most important issues that suppliers of RF transmitters have to face in the next years. The class-S concept is seen as an attractive solution to both – power efficiency and multi-standard, multi-band operation [1, 2]. In a transmission chain with class-S concept the conventional linear PA is replaced by a power efficient switching-mode amplifier. The pulse sequence for the switching-mode amplifier input is generated from the analog RF-signal by a continuous-time bandpass delta-sigma modulator (CT-BPDSM). A bandpass filter reconstructs the analog signal at the output of the PA (Fig. 1). In the long term digital delta-sigma signal processing in CMOS [3, 4] with upsampling from base band to the switching-mode amplifier input is considered as both cost- and energy-efficient. However, the required clock frequency for signal frequencies above 2 GHz is not reached yet with current CMOS technologies. With a continuous-time BPDSM higher signal frequencies can be achieved due to fast analog signal processing. As an analog RF input signal is required, only the PA is replaced by the switching mode amplifier and the reconstruction filter in the transmission chain. This allows for upgrades of existing RF transmitters. As well, CT-BPDSMs remain the only solution for modulators in class-S amplifiers with signal frequencies well beyond 2 GHz in the near future. The experimental results of a CT-BPDSM with a fixed center frequency at 2.2 GHz will be presented elsewhere [5]. This work describes a CT-BPDSM for multiband operation. The paper is organized as follows: In Section II the architecture of the modulator and the most important circuit blocks are described. Measurement results are presented in Section III and in Section IV a short conclusion is given. Figure 1. Block diagram of a class-S power amplifier II. CIRCUIT DESIGN A. System architecture Fig. 2 shows the block diagram of the circuit. A multi- feedback architecture with RZ and HRZ pulses is used for the modulator [6]. HRZ pulses are generated by a latch with a subsequent RZ latch. The feedback currents k 1r , k 1h , k 2r and k 2h can be controlled by externally applied currents via current mirrors. 978-1-4244-3376-6/978-1-4244-3378-0/09/$25.00  2009 IEEE 2009 IEEE Radio Frequency Integrated Circuits Symposium RMO2C-4 153