International Journal of Electrical and Computer Engineering (IJECE) Vol. 3, No. 6, December 2013, pp. 805~814 ISSN: 2088-8708  805 Journal homepage: http://iaesjournal.com/online/index.php/IJECE Evaluation of High Speed Hardware Multipliers - Fixed Point and Floating point Awais Ahmed 1 , Syed Haider Abbas 2 , Muhammad Faheem Siddique 2 , Hussnain Haider 2 1 School of Electrical Engineering, University of Faisalabad, Pakistan 2 Departement of Electrical Engineering, Sarhad University of Science and IT, Pakistan Article Info ABSTRACT Article history: Received Aug 11, 2013 Revised Oct 14, 2013 Accepted Nov 1, 2013 There is a huge demand in high speed arithmetic blocks, due to increased performance of processing units. For higher frequency clocks of the system, the arithmetic blocks must keep pace with greater requirement of more computational power. Area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. In our research we will try to determine the best solution to this problem by comparing the results of different multipliers. Different sized of two algorithms for high speed hardware multipliers were studied and implemented ie. Parallel multiplier, Bit serial multiplier. The workings of these two multipliers were compared by implementing each of them separately in VHDL. A number of high speed adder designs are developed and algorithm and design of these adders are discussed. The result of this research will help us to choose the better option between serial and parallel multipliers for both fixed point and floating point multipliers to fabricate in different systems. As multipliers form one of the most important components of many systems, analysing different multipliers will help us to frame a better system with area and better speed. Keyword: Bit Serial Multiplier Fixed Point Floating Point Parallel Multiplier VHDL Copyright © 2013 Institute of Advanced Engineering and Science. All rights reserved. Corresponding Author: Syed Haider Abbas Departement of Electrical Engineering, Sarhad University of Science and Information Technology, Hayatabad Link, Ring Road, Peshawar, Pakistan Email: habbas33@gmail.com 1. INTRODUCTION Multipliers are the major components of high performance systems used extensively in digital electronics such as microprocessors, digital signal processors and FIR Filters etc. The performance of any system is determined by the performance of multipliers because they are the slowest part in the system. Moreover, they require greater area than other components. Therefore, optimizing the speed and area of the multipliers is the foremost issue. As area and speed are both conflicting constraints this means that for greater speed we need larger area. A number of algorithms are proposed and used to design multipliers and the actual implementation is mostly some little refinements and variations of the few basic algorithms presented here. In addition to choosing those algorithms for addition, subtraction, multiplication etc an architect must make other decisions like how exceptions should be handled and what precisions should be implemented. We have designed two typed of multiplier for fixed and floating point [1-2]. Our discussion on floating point will focus almost exclusively on the IEEE floating-point standard (IEEE 754) because of its rapidly increasing acceptance. Although floating point arithmetic involves manipulating exponents and shifting fractions, the bulk of the time in floating point is spent operating on fractions using integer algorithms. Thus, after our discussion of floating point we will take a more detailed look at efficient algorithms and architectures. brought to you by CORE View metadata, citation and similar papers at core.ac.uk provided by Institute of Advanced Engineering and Science