Riya Saini, Galani Tina G. and R.D. Daruwala 12 International Journal of Emerging Trends in Electrical and Electronics (IJETEE – ISSN: 2320-9569) Vol. 5, Issue. 1, July-2013. Efficient Implementation of Pipelined Double Precision Floating Point Unit on FPGA Riya Saini, Galani Tina G. and R.D. Daruwala Abstract: The arithmetic circuits are the most fundamental blocks which are used to build DSP [9] hardware. Traditionally, digital signal processing (DSP) is performed using fixed-point or integer arithmetic. Use of floating-point arithmetic provides a large dynamic range. Floating-point representation is able to retain its resolution and accuracy compared to fixed-point representations. Unfortunately, floating point operators require excessive area (or time) for conventional implementations. Here we introduce a pipeline floating point arithmetic logic unit (ALU).Pipeline is used to give high performance and throughput to arithmetic operation. In this paper an arithmetic unit based on IEEE standard for floating point numbers has been implemented on FPGA Board. The arithmetic unit implemented has a 64- bit pipeline processing unit which allows various arithmetic operations such as, Addition, Subtraction, Multiplication and Division on floating point numbers. All the modules in the ALU design are realized using VHDL. Design functionalities are validated through simulation and compilation. The throughput is increased by pipelining the designed unit. This design unit is mapped onto Vertex 4 XC4VLX40 FPGA in order to achieve higher data rates. Comparative analysis is done between pipeline and sequential approach in terms of speed, power, throughput, latency and chip area. Keywords: Floating Point Unit, FPGA, VHDL, Xilinx ISE 12.1. I. INTRODUCTION The reconfigurability and programmability of Field Programmable Gate Arrays (FPGAs) make them attractive tools for implementing digital signal processing (DSP) applications. However, DSP applications are arithmetic intensive tasks, requiring in most cases floating point operations to be performed as part of the application itself. As demand rises for electronic devices to be smaller, faster and more efficient, increasing importance is placed on well designed pipelined architecture. Pipelined architecture that uses concurrent processing tends to use faster clock period, less combinational delay and hence faster speed but also consumes more chip area compared with standard architecture(without pipeline) that uses sequential processing. Pipelining is directly proportional to chip area. As stages of pipelining increases there is increase in throughput but with an adverse effect of increase in chip area. Riya Saini, Galani Tina G. are M.Tech Student, dept. of Electrical Engineering, VJTI, Matunga, Mumbai-19 and R. D. Daruwala is working as Professor, dept. of Electrical Engineering, VJTI, Matunga, Mumbai-19, Emails: sainiriya993@gmail.com The IEEE standard for binary floating-point arithmetic [2] provides a detailed description of the floating-point representation and the specifications for the various floating-point operations. It also specifies the method to handle special cases and exceptions. In this paper an arithmetic unit based on IEEE standard for floating point numbers has been implemented on FPGA. The arithmetic unit implemented has a 64- bit pipeline processing unit. All the modules in the ALU design are realized using VHDL. We implemented our design using Xilinx ISE 12.1, with Xilinx Virtex-4 XC4VLX40 FPGA as our target device. In the top-down design approach, four arithmetic modules: addition, subtraction, multiplication, and division: are combined to form the floating-point ALU. The pipeline modules are independent of each other. The organization of this paper is as follows: Section 2 describes background on floating point representation. Section 3 describes algorithm used by each module in design of floating point unit. Section 4 describes our approach in design of FPU. The simulation environment and results are summarized in Section 5 and concluding remarks are discussed in Section 6. II. BACKGROUND A. Floating Point Representation Standard floating point numbers are represented using an exponent and a mantissa in the following format: (sign bit) mantissa × base exponent +bias The mantissa is a binary, positive fixed-point value. Generally, the fixed point is located after the first bit, m0, so that mantissa = {m0.m1m2...mn}, where mi is the ith bit of the mantissa. The floating point number is “normalized” when m0 is one. The exponent, combined with a bias, sets the range of representable values. A common value for the bias is −2k−1, where k is the bit-width of the exponent [4].The double precision floating point format has an 11 bit exponent and 52 bit mantissa plus a sign bit. This provides a wide dynamic range. Fig 1.64-bit Floating Point Format The sign bit occupies bit 63. ‘1’ signifies a negative number, and ‘0’ is a positive number. The exponent field is 11 bits long, occupying bits 62-52. The value in this 11-bit