Indian Journal of Science and Technology, Vol 10(1), DOI: 10.17485/ijst/2017/v10i1/110286 January 2017 ISSN (Print) : 0974-6846 ISSN (Online) : 0974-5645 * Author for correspondence 1. Introduction In past decade, most of computer components integrated in single silicon chip i.e. System on Chip (SoC). It has contained powerful processors, analog, digital and mixed signal components on a silicon substrate. SoC mainly used in embedded applications. Te foremost problem of these components is communication between them 1 . If the number of components has increased, communication between components has considerably complex. Communication networks are connecting diferent geographically distributed points. In point to point communication, the connection of the any two resources is fxed. It provides fexibility with avoiding arbitration but some resources have not involved for processing data. It had been leading a problem of less utilized resources while to increase resource utilization, bus based on chip communication has introduced. In bus technology, components are connected with a single bus. It is simple and widely used as components are connected through bus. Due to a single bus, servicing of components has been delayed and consumed much power. It is not scalable as the bandwidth has shared to entire system resources. To overcome the problem, hierarchical bus has used. Bridge has attached between the multiple buses and saved the power consumption due to the not using long wires. Tis technique having multiple buses which leads arbitration between buses and numerous wires connected to the bus. To solve arbitration overhead, bus matrix method has introduced. Te resources are connected in a matrix manner. By using matrix bus, the arbitration has overcome but due to on chip interconnects electric noise, degrading performance, energy consumption and scalability increased. Tese problems have been given a new paradigm i.e. NoC. Dally 2 and Benini 3 have introduced this new on chip communication for SoC. NoC is the system which consists of a group of routers with Processing Elements (PEs) and formed a topology (ex. Mesh, torus, folded torus, tree/fat tree and ring). While transferring data, source router connects other router through PE until it reaches to its destination router. PEs has controlling the data transmission over the fits or dedicated channels. NoC has been giving notable improvements over the conventional bus and the sharing Abstract Objectives: Network on Chip (NoC) has been emerging area as communication is very complex at Chip Multi Processor and it has become more popular due to its high bandwidth and improved performance than System on Chip (SoC). Methods: This paper gives an overview of various proposals and discussed some methods for NoC and various types of topologies and types of switching techniques have given with their merits and demerits. The routing algorithms are given based on adaptively which finds the shortest distance from source to destination. Findings: This paper proposes a new architecture for low latency and low area NoC router by analyzing the different architectures for NoC by observing the number of architectures. The generic NoC has used with packet switching and deterministic routing algorithm but new techniques implemented for the routing algorithms i.e. shortest path, odd/even, north-east and south-west. Application/Improvements: NoC has improved performance that’s why it has applied in various systems, JPEG decompression, wireless transmission and security systems. Keywords: FPGA, NoC, Routing, Switching, Topology A Survey for Silicon on Chip Communication K. Ashok Kumar * and P. Dananjayan Department of ECE, Pondicherry Engineering College, Puducherry - 605014, India; kashok483@pec.edu, pdananjayan@pec.edu