Through-Silicon-Via Management during 3D Physical Design: When to Add and How Many? Mohit Pathak, Young-Joon Lee, Thomas Moon, and Sung Kyu Lim School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, Georgia, USA {mohitp, yjlee, tmoon, limsk}@gatech.edu Abstract— In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger area than regular gates. In this paper, we address two critical aspects of TSV management in 3D designs. First, we address the problem of how many TSVs to add in a design. Since TSVs occupy significant silicon area, a general tendency has been to use a minimum number of TSVs in 3D circuits. We show that such an approach does not give us the best possible result. Second, we address the problem of TSV insertion. Because TSVs occupy silicon area, their location is decided during the placement stage of 3D design. However, we show that this is not the best possible stage for TSV insertion. We propose a change in the physical design flow for 3D integrated circuits to address the limitations of existing TSV placement methodology. All our algorithms are integrated with commercial tools, and our results are validated based on actual GDSII layouts. Our experimental results show the effectiveness of our methods. I. I NTRODUCTION Technology scaling has enabled smaller and faster devices thus increasing integration density and decreasing intrinsic gate delay. Higher integration density requires a greater num- ber of longer interconnects. Therefore, as the device delay is reduced, the performance of the circuit becomes dominated by the interconnect delay. In addition, other interconnect related issues, such as power consumption and signal integrity, have become more pronounced with technology scaling. To manage these issues three dimensional integration has been proposed [1]. The emerging 3D die stack technology enables the integration of multiple planar integrated circuits in the vertical direction with high density interconnect using TSVs. Various methods exist for the fabrication of TSVs for stacked 3D ICs [1]. The two most popular methods are (i) via first, and (ii) via last. In the via first method, blind vias, which do not go all the way through the wafer, are formed in the wafer before transistors are created or immediately after. The wafer is thinned from the backside until the TSVs are exposed, then the next wafer can be attached to the back of the thinned wafer. In the via last approach, individual chips with transistors and interconnects already formed are stacked on top of each other. The vias are then etched from the back of the face-down chip reaching down to the bond pads of the front. TSVs with 2 diameter and 7 pitch have been fabricated using the This material is based upon work supported by the National Science Foundation under CAREER Grant No. CCF-0546382, the SRC Interconnect Focus Center (IFC), and Intel Corporation. SRAM cell inverter TSV TSV landing pad TSV keep-out zone Fig. 1. Size comparison among SRAM cell, INV, and via-first TSV in 45nm via last method thus allowing large number of TSVs [1]. TSVs are several times larger than logic gates and memory cells as illustrated in Figure 1 . Therefore it is critical to consider the impact of TSVs while designing 3D ICs. In this paper we consider the via first fabrication process. A large amount of work has been done on placement in 3D integrated circuits. The authors of [2] extend the analytical placement in 2D ICs to 3D ICs, however they do not consider the area impact of through silicon vias resulting in a large number of TSVs. The works done by authors in [3], [4] and [5] also ignore the impact of through silicon vias on area and report unacceptably large via count. The authors in [6] discuss the impact of partitioning on 3D floor planning and the authors in [7] use partitioning driven 3D IC placement. However, both these works fail to show the impact of through silicon via size on 3D ICs. The authors in [8] provide the first detailed placement and routing results for 3D ICs that demonstrates GDSII based layout. The authors show that through silicon vias can have a significant impact on the area and wire length of a circuit. They first perform a simple partitioning of the circuit followed by force directed 3D placement. In some cases the authors claim that 3D ICs result in wire-length worse than 2D ICs. However, they do not provide details of how they perform initial circuit partitioning into different dies. 3D technology can help in reducing the problem of long interconnect lengths in 2D ICs. However determining the num- ber and locations of TSVs is very important. TSVs typically have much larger size than standard cells. Thus using too 978-1-4244-819 - /10/$26.00 ©2010 IEEE 387 41