Synthesis of Testable Pipelined Datapaths using Genetic Search C.P. Ravikumar Department of Electrical Engineering Indian Institute of Technology Hauz Khas, New Delhi INDIA V. Saxena * Department of ECE University of Illinois at Urbana Champaign Urbana, IL USA Abstract In this paper, we describe TOGAPS, a Testability- Oriented Genetic Algorithm for Pipeline Synthesis. The input to TOGAPS is an unscheduled data flow graph along with a specification of the desired pipeline latency. TOGAPS generates a register-level descrip- tion of a datapath which is near-optimal in terms of area, meets the latency requirement, and is highly testable. Genetic search is employed to explore a 3- D search space, the three dimensions being the chip area, average latency, and the testability of the datap- ath. Testability of a design is evaluated by counting the number of self-loops in the structure graph of the data path. Each design is characterized by a four-tuple con- sisting of (i) the latency and schedule information, (ii) the module allocation, (iii) operation-to-module bind- ing, and (iv) value-to-register binding. An initial pop- ulation of designs is constructed from the given data flow graph using different latency cycles whose average latency is in the specified range. Multiple scheduling heuristics are used to generate schedules for the DFG. For each of the resulting scheduled data flow graphs, we decide on an allocation of modules and registers based on a lower bound estimated using the sched- ule and latency information. The operation-to-module binding and the value-to-register binding are then car- ried out. A fitness measure is evaluated for each of the resulting data paths; this fitness measure includes one component for each of the three search dimensions. We have implemented TOGAPS on a Sun/SPARC 10 and studied its performance on a number of benchmark examples. Results indicate that TOGAPS finds area- optimal datapaths for the specified latency cycle, while reducing the number of self-loops in the data path. 1 Introduction The synthesis problem has been studied extensively in the recent past [5]. Our approach is different from the existing techniques in the following ways. We eval- uate designs on not only area and time performance, but on structural testability properties as well. We use a genetic algorithm for exploring the 3-D design space characterized by area, time, and testability. Earlier efforts in datapath have concentrated chiefly on minimization of chip area subject to timing con- *This author was a B.Tech student of IIT Delhi in EE De- partment when this work was carried out. straints [3, 8, 9]. Recently, testability of the generated datapath has assumed importance [1, 6, 7]. Papachris- tou et al. introduced testable logic blocks ?TLB) in the construction of testable datapaths [7]. A TLB consists of a combinational logic block fed from a register Rl and feeding another register R2. In test mode, register Rl can be configured as a test pattern generator and R2 can be configured as a signature analyzer. Simple rules are defined in [7] to interconnect TLBs without forming self loops in the structure graph of the data- path. The structure graph of a datapath is a graph whose nodes correspond to registers in the datapath. A directed edge is drawn from a node i to node j if input of register j can be reached from output of reg- ister i through a purely combinational path. A self- loop involving a node i in the structure graph implies poor testability, requiring the register i be configured as a pattern generator and a signature analyzer at the same time, an impossibility unless an area-expensive concurrent BILBO is used [1, 7]. The binding phase in the synthesis process is most crucial in minimizing the number of self-loops in the structure graph. Avra [1] generates register bindings to minimize the number of self-loops without altering module binding. Mujumdar et al. use a network flow algorithm to carry out module and register bindings that minimize the number of self- loops [6]; they also proposed loop-breaking algorithms to further improve the testability of the resulting data- path. Existing approaches for testability-oriented syn- thesis address the problem of improving testability at the binding level; performance optimizations are first carried out using conventional scheduling and alloca- tion heuristics. In TOGAPS, we address testability and area-time optimization in an integrated fashion at all the levels, namely, scheduling, allocation, and bind- ing. To consider all the three design parameters simul- taneously, we use a genetic algorithm, a powerful tool for exploring a large design space. Section 2 describes the genetic algorithm for pipeline synthesis. In Section 3, we discuss the genetic opera- tors (crossover and mutation) used in TOGAPS. The cost functions used in TOGAPS, and the techniques used to prune the large design space are discussed in Section 4. Experimental results are described in 5 and conclusions in Section 6. 205 9th International Conference on VLSI Design — January 1996