Copyright © 2018 Authors. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. International Journal of Engineering &Technology, 7 (3.12) (2018) 759 -763 International Journal of Engineering & Technology Website: www.sciencepubco.com/index.php/IJET Research paper Design and Analysis of 8-bit Vedic Multiplier in 90nm Technology using GDI Technique Sandesh Sharma 1 , Vangmayee Sharda 2 Amity University, Uttar Pradesh, India. *Corresponding Author Email: 1 sandeshsharma01@gmail.com, 2 vsharma3@amity.edu Abstract Vedic mathematics is an old mathematics which is more effective than other mathematic procedures. Vedic maths is utilized as a part of numerous applications, for example, hypothesis of numbers, compound duplications, squaring, cubing, square root and solid shape root and so on. Absolutely there are 16 sutras and 14 sub-sutras in Vedic maths. Among those sutras, just 3 sutras and 2 sub-sutras are utilized for augmentation. Multiplier is a very important part of a microprocessor as multiplication is performed continuously in all calculative procedures. This paper is in importance of a 8-bit multiplier designed in 90 nm technology. Urdhva-Tiryakbyham is the sutra that is used for multiplication in Vedic mathematics. Actualizing the different scientific operations utilizing Vedic Mathematics causes us accomplish better speed, bring down unpredictability and higher execution.[2] The technique used is Gate Diffusion Input (GDI) which is a more refined way to design a circuit which less complex than circuits designed by other techniques. Index Terms: Vedic Multiplier, Urdhva-Tiryakbyham, Gate Diffusion Input, 90 nm technology. 1. Introduction In this fast pacing world of advancing science and technology, when we talk about vedic multipliers, a lot of research has been done and as a matter of fact already been going on. This is because of the importance of results that researchers have gotten but there is always a scope. In this paper 8-bit vedic multiplier is designed using GDI technique in 90 nm technology. The most vital requirement of any processor would be Speed, Area and power which are also the three pillars of VLSI. The design Proposed in this paper would give us a circuit which will have high speed, reduction in delay and it would consume less power. The circuit made will be performing in an improved manner because of the usage of vedic mathematics and gate diffusion input. When we talk about processors like FFT, DSP convolution, IDFT and many others, multiplier is considered as the the foundation stone. In Laymen language a multiplier is something that would give us multiple outputs when lesser inputs are provided or in other words, a number by which the other number is multiplied. For every processor to have higher speed, a high speed multiplier is suggested. The higher the speed of the multiplier would be , the more efficient will the processor worked out to be. Research has shown that whenever we switch to vedic multiplier, all these concerns can be satisfied. The most popular sutras of vedic mathematics are Urdhva- Tiryakbhyam and Nikhilam sutra (names derived from Sanskrit) but when it comes for the multiplication or in this case use of a multipier, the most appropriate sutra to be used will be the UT (Urdhva-Tiryakbhyam) sutra. Hence in this paper only this sutra is used and discussed. [1] In a vedic multiplier using GDI, vedic multiplication comprises of AND gates, half adders and full adders. Vedic multiplication requires less processing time for the execution that‟s why it has been used here as it is a sturdy way of multiplication. It makes the use of less number of transistors in comparison to C-MOS. Realizing these functions using CMOS requires 6-12 transistors. But the same functions are very easy to implement using GDI method and require only two transistors per function. 2. Technologies Used Gate Diffusion Input (GDI) GDI can be described as a method of less-power circuit integration. With this method we can reduce power consumption, propagation delay, and area with a less complex circuit. If we compare the traditional CMOS design and the GDI circuit, we can easily see the difference in terms of power consumption. The layout area, number of devices, delay, and power dissipation are the factors that are directly affected as we use gate diffusion input logics.[6] Technology adaptability, better design, and precomputing amalgamation are some of the issues that have come into light, presenting the pros and cons of GDI to other techniques. The paper shows a upgraded low-power design technique that solves the major problems mentioned in the introduction. The GDI method permits the execution of bulks of complicated logic functions by the use of only two transistors. The basic GDI cell can be seen and the basic functions of a GDI cell can be understood.[6]