SILICON DEBUG AND DIAGNOSIS Debug enhancements in assertion-checker generation M. Boule ´ , J.-S. Chenard and Z. Zilic Abstract: Although assertions are a great tool for aiding debugging in the design and implemen- tation verification stages, their use in silicon debug has been limited so far. A set of techniques for debugging with the assertions in either pre-silicon or post-silicon scenarios are discussed. Presented are features such as assertion threading, activity monitors, assertion and cover counters and completion mode assertions. The common goal of these checker enhancements is to provide better and more diversified ways to achieve visibility within the assertion circuits, which, in turn, lead to more efficient circuit debugging. Experimental results show that such modifications can be done with modest checker hardware overhead. 1 Introduction Techniques for post-fabrication debugging, known as silicon debugging, are receiving much attention, as increas- ing transistor counts and smaller process technologies make it difficult to achieve correct silicon. Companies such as DAFCA, for example, allow the addition of register transfer level (RTL) silicon-debug instrumentation to the source design, the status of which can be read back through the Joint Test Action Group (JTAG) interface [1]. Examples of useful debug instruments that are implemented in their tools are: in-circuit trace buffers for capturing signals or supplying vectors, signal probe multiplexers and logic ana- lyser circuitry. To ensure flexibility in providing these post- silicon debug instruments, they are implemented in small blocks of added programmable logic gates. The debugging instruments [1] and the checker enhancements presented in this paper encompass a collection of techniques that share a common goal, to help increase the efficiency of the debug- ging process. The boldface numbers in the tables show the best result for each test case. For FFs and LUTs, lower is better; for speed (MHz), higher is better. Verification aims at eliminating errors before tape-out, by ensuring that a design follows its intended specification. Assertion-based verification (ABV) is a relatively new methodology that is becoming increasingly important [2]. Assertions are meant to express intended circuit functional- ity in a formal language. The two most common assertion languages are the property specification language (PSL) and SystemVerilog assertions (SVA). Assertion failures reveal design errors either through formal or simulation- based verification, and are an important failure localisation mechanism aiding the debugging process. Increasingly, formal verification tools and simulators are able to interpret assertions, which help pinpoint design errors before fabrica- tion. Assertions can also be used in hardware emulation or simulation accelerators; however, descriptions in high-level assertion languages are not easily converted into efficient RTL descriptions suitable for emulation platforms, such as FPGA-based emulators. To exploit the power of asser- tions in hardware form, a checker generator [3] was designed to create efficient circuit-level checkers from assertion statements. These checkers monitor the device under verification (DUV) for violations of assertions and raise an output signal when a violation is observed. Circuit-level assertion checkers can be used not only for pre-fabrication verification, but also for post-fabrication silicon debugging (Fig. 1). Assertion checkers can be purpo- sely added to the synthesised design to increase debug visi- bility during initial testing of the IC. Assertions compiled with a checker generator can also be used as on-line circuits for various in-field status monitoring purposes, as shown in the right side of Fig. 1. In the emerging design for debug (DFD) space, several companies are promoting a range of solutions. Tools from companies such as Novas now support advanced debugging methods to help find the root cause(s) of errors by back- tracing assertion failures in the RTL code [4]. Temento’s DiaLite product accepts assertions and provides in-circuit debugging features. DAFCA also offers this possibility, and provides support for assertion checker synthesis and use. However, as these tools are from commercial ventures, papers seldom disclose their actual inner-workings. Increasing and enhancing the visibility into the design’s signals is also an important aspect in silicon debugging and DFD [5]. In this paper, increasing visibility using ABV techniques is explored. More specifically, this work presents the techniques that enhance assertion checkers with several debug features [6]: hardware coverage moni- tors, activity tracers, assertion completion and assertion threading. These enhancements improve the debugging capabilities of the resulting checkers in all scenarios in shown Fig. 1. In verification and silicon debugging, the enhancements offer the means to help pinpoint the exact cause of an assertion failure. In the on-line monitoring scenario, the assertion completion mode and the activity monitors can play a key role in creating checkers that evaluate the quality of a circuit for in-field, real-time diagnosis. All debugging enhancements are implemented in our checker generator called MBAC, where they can be # The Institution of Engineering and Technology 2007 doi:10.1049/iet-cdt:20060209 Paper first received 21st November 2006 and in revised form 20th July 2007 The authors are with the McGill University, Montre ´al, Que ´bec, Canada E-mail: marc.boule@elf.mcgill.ca IET Comput. Digit. Tech., 2007, 1, (6), pp. 669–677 669