Journal of VLSI Signal Processing, 4, 213-226 (1992) 9 1992 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands. DDFSGEN A Silicon Compiler for Direct Digital Frequency Synthesizers LINDA KWAI-LIN LAU, RAJEEV JAIN, HENRY SAMUELI, HENRY T. NICHOLAS, III AND ETAN G. COHEN Electrical Engineering Department, UCLA, Los Angeles, CA 90024 Received March 15, 1991; Revised October. 15, 1991. Abstract. This paper presents a functional compiler for the automatic design of Direct Digital Frequency Syn- thesizer (DDFS) integrated circuits (ICs) using a ROM based table look-up architecture. The compiler allows the user to specify high-level specifications such as the acceptable spurious response and it generates the IC arch- itecture, floorplan, and layout. To construct the layout for different specifications, a library of parameterized macrocells has been developed in 1.2/~m CMOS technology. A test chip with a quadrature DDFS module has been generated, using the compiler, and fabricated. The chip has two input signals: one is for frequency control while the other is for phase initialization. Input and output word lengths are 16 bits and 6 bits respectively. The chip complexity is approximately 12,000 transistors (DDFS core) and the die size is 4.8 • 2.9 mm 2. A maximum sample rate of 80 MHz has been attained implying a max- imum sine (cosine) output frequency of 40 MHz and a frequency resolution of 1.22 kHz. The maximum spurious level measured is -46 dB. 1. Introduction Direct Digital Frequency Synthesis (DDFS) is desirable in high performance digital communication applications because of its many advantages such as high resolu- tion, good spectral purity, and fast switching speed. While commercial DDFS integrated circuits are cur- rently available, they are only point solutions, suitable for specific applications, and are not always optimal. Furthermore, in many applications it is now possible and desirable to integrate the DDFS module along with other components of a communication device onto a single chip. To satisfy a wide range of applications of the DDFS, a functional compiler, DDFSGEN, is presented in this paper that generates DDFS integrated circuit layouts from high-level specifications such as spurious response and frequency resolution. The layout can be fabricated as a stand-alone chip or it can be combined with other circuit modules using the VANDA design system [1] to generate a complex chip such as a receiver [2]. For automatic generation of functional blocks such as the DDFS, general purpose techniques like logic syn- thesis would not be as efficient as a dedicated compiler. It would also be difficult to translate the functional specifications of the DDFS into a logic expression suitable for logic synthesis tools. The logic expression would have to generate sine wave samples with a desired spurious level. Two ICs have been designed and fabricated using the DDFSGEN functional compiler: the first is a DDFS chip with a maximum sample rate of 80 MHz and a spur level of -46 dB; the second is a Costas loop BPSK re- ceiver chip [2] that incorporates the DDFS along with other components. Both chips have been tested and found functional. Circuits designed with DDFSGEN can gen- erate quadrature outputs with a spurious response in the range of -45 to -90 dB and can operate at sample rates of 50 to 85 MHz with a 1.2 micron CMOS library. Higher frequencies can be achieved with a more ag- gressive cell library. The frequency and phase of the output sine wave can be independently controlled. 1.1. Computer-Aided Design Environment DDFSGEN has been interfaced to VANDA [1], a com- puter aided design environment for communication signal processing systems. This environment allows different compilers to be used in combinations with parameterized macrocells and standard cells to design, simulate and generate IC layouts for communication sub-systems such as transceivers. The block schematic