A 60-MHz 64-TAP ECHO zyxwvutsrq CANCELLER/DECISION-FEEDBACK EQUALIZER IN 1.2-pm CMOS FOR 2B1Q HIGH BIT-RATE DIGITAL SUBSCRIBER LINE TRANSCEIVERS Henry Samueli, Robindra B. Joshi, Bennett C. Wong, Babak Daneshrad, Loke Kun Tan, David Kruse and Henry T. Nicholas Integrated Circuits and Systems Laboratory Electrical Engineering Department University of Califomia, Los Angeles ABSTRACT A 60-MHz 64-tap adaptive FIR filter chip has been fabricated in 1.2-p.m CMOS which can implement either an Echo Canceller or Decision-FeedbackEqualizer for 2BlQ High Bit- Rate zyxwvutsrqp Di ital SubscriberLine (HDSL) transceivers. The 4.3 x adaptive filter which incorporates the L%S algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths which are often required in high bit-rate transceivers. At a 60-MHz clock rate the Echo CancellerDecision Feedback Equalizer chip can accommodate symbol rates in excess of 800 kbaud. 4.3 mm zyxwvutsrqp 1 zyxwvuts , 30,000 transistor chip is a com lete self-contained I. INTRODUCTION Bellcore has recently initiated an effort to determine the feasibility of delivering T-1 data rates (1.544 Mb/s) over existing twisted-pair copper loops at ranges up to 9 kft. of 26 AWG cable or 12 kft. of 24 AWG cable without repeaters. The so- called High Bit-Rate Digital Subscriber Line (I-IDSL) transceiver must be able to operate over unconditioned copper loops; that is, loops with bridge taps and gauge changes. The impedance mismatches introduced by the bridge taps and gauge changes along with the pulse spreading which results from the lowpass response of the loop significantly degrades the transmitted signal, therefore the transceiver must use adaptive equalization to correct for these impairments. Furthermore, bi-directional transmission is desired over each wire pair which requires the use of adaptive echo cancellation. These signal processing techniques have been applied successfully to 160 kb/s ISDN Basic-Rate transceivers to accommodate ranges up to 18 kft., and several single chip transceivers are now commercially available [l, 21. In this paper we present a CMOS device which implements these signal processing algorithms for HDSL transceivers operating at 800 kb/s. Two full-duplex 800 kb/s transceivers operating in parallel on two copper loops are therefore sufficient to accommodate the 1.544 Mb/s T-1 data rate. This approach is commonly referred to as a dual-duplex approach. The 2B 1Q line code has been adopted as the North American standard for ISDN basic-rate (160 kb/s) digital subscriber lines [3]. 2B1Q (2 Binary, 1 Quaternary) is a baseband 4-level Pulse Amplitude Modulation (4-PAM) code for which each pair of binary data bits is mapped into a quaternary (4-level)symbol. A 400 kbaud symbol rate is required to achieve a data rate of 800 kb/s using a 2B1Q line code. Shown in Fig. 1 is an example of a typical receive pulse (provided by Bellcore) resulting from passing a 2.5-psec square pulse through a transmit filter, transmit transformer, 9 kft., 26 AWG loop, receive transformer and receive filter. The peak of the pulse is attenuated by approximately 27 dB and the tail of the pulse decays to 1% of the peak after approximately 250 psec (100 baud intervals). 120 L ' . . . , . , , . . . . , . . , , . . . , . . . 100 E zyxwvutsrqp 60 v zyxwv 0 3 k 40 a I . z 20 0 0 50 100 150 200 250 300 TIME (microsec) Fig. 1 Pulse waveform at output of 9 kft. 26 AWG loop. This excessive pulse spreading indicates that very long echo cancellers and decision-feedback equalizers (greater than 100 taps) will be required to achieve satisfactory performance in a 2B 1Q HDSL transceiver implementation. A block diagram of an HDSL receiver architecture incorporating an echo-canceller (EC) and decision-feedbackequalizer (DFE) is shown in Fig. 2. The EC and DE are, by far, the most computation intensive blocks in the HDSL receiver. Section I1 describes the architecture of the Echo CancellerDecision-Feedback Equalizer (ECDFE) chip which implements these two critical adaptive filtering functions, and the test results of the chip are presented in Section ID. 7.2.1 IEEE 1991 CUSTOM INTEGRATED CIRCUITS CONFERENCE Fig. 2. Simplified block diagram of 2B 1 Q HDSL receiver. 11. EC/DFE CHIP ARCHITECTURE A simplified block diagram of the EC/DFE is shown in Fig. 3. The EC/DFE chip accepts a new 2-bit data symbol and a 16- bit error input each symbol period, and produces a 16-bit echo estimate (for EC applications) or IS1 estimate (for DFE applications) during the same symbol period. In addition, all filter coefficients are updated in every symbol period using a CH2994-2/91/0000/0026 $1.00 1991 IEEE .