IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 28, NO. 1, JANUARY 2018 67 Layout and Interconnect Optimization for Low-Power and High-Sensitivity Operation of E -Band SiGe HBT Frequency Dividers Aleksey Dyskin , Parisa Harati, and Ingmar Kallfass Abstract—A layout and interconnect optimization techniques for low-power and high-sensitivity performance of static fre- quency dividers in E-band is reported. The layout optimization provides optimal transistor placement and identifies critical interconnects, which allows to reduce their parasitics. These measures provide high operation frequency and good sensitivity of the divider without a need of investing additional dc current. Index Terms— E-band, frequency divider, layout optimization, millimeter wave (mmw) integrated circuits, silicon– germanium (SiGe). I. I NTRODUCTION R ECENT advances in millimeter wave (mmw) radio links dictate strong demand of integrated receivers capable of demodulating high-frequency and wide bandwidth modulated signals. The essential building block of such receivers is a frequency divider circuit, used in phase-locked loop imple- mentation [1], quadrature signal generation [2], and carrier- recovery techniques [3]. The self-oscillation frequency (SOF) is often used as a divider performance figure of merit (FOM). The trade-off between frequency of operation, input sensi- tivity, and power consumption raises several design considera- tions. Static (digital) dividers employ an emitter-coupled logic master-slave latch to achieve the frequency division. These dividers sport an SOF in the vicinity of the half-rate frequency and thus have good sensitivity. To achieve higher operation frequencies, static dividers are biased with relatively high dc currents, causing high power consumption. In the low-power application era, this major drawback should be addressed. One way to enhance the SOF and to preserve low current consumption is the widely used inductive peaking technique [4]. Stacked inductors can be used to save chip area, but the self-resonance frequency of these inductors should be carefully considered. Another method to achieve high SOF is to use the asymmetric latch pair [5]. The main drawbacks of this technique are degraded sensitivity at lower frequencies and high common noise sensitivity. Manuscript received September 18, 2017; accepted November 2, 2017. Date of publication December 4, 2017; date of current version January 8, 2018. (Corresponding author: Aleksey Dyskin.) A. Dyskin is with the Department of Electrical Engineering, Technion-Israel Institute of Technology, Haifa 3200003, Israel (e-mail: aleksd@campus.technion.ac.il). P. Harati and I. Kallfass are with the Institute of Robust Power Semicon- ductor Systems, University of Stuttgart, 70174 Stuttgart, Germany (e-mail: ingmar.kallfass@ilh.uni-stuttgart.de). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LMWC.2017.2772169 Fig. 1. Divider by two microphotograph (0.18 × 0.15 mm 2 excluding pads). This letter presents a layout and interconnect optimization technique of the static divider design, performed in a SiGe BiCMOS 0.13-μm process by Leibniz-Institut für innovative Mikroelektronik, featuring f T / f max of 250/330 GHz (Fig. 1). The divider is inductorless, employing the split-resistor load topology to enhance the SOF [6]. To examine the technique, two dividers were fabricated: an optimized divider, based on the proposed optimization technique; and a reference divider, produced with suboptimal transistor and interconnects placement. The experimental results demonstrate that even small deviations from the proposed layout degrade the divider performance. II. DIVIDER OPTIMIZATION The SOF is a frequency at which zero clock swing results in an output signal at the half-rate frequency. With zero clock swing, the divider can be seen as a two-stage ring oscillator. The SOF can be then predicted as a phase crossover frequency according to the Barkhausen stability criterion. The main contributors to the phase crossover are the dominant poles of two D-latches. The dominant pole can be estimated by zero- value time constant method [7]. Identifying the interconnect delays by τ , the dominant pole is given by (Fig. 2(a)) ω p ≈[τ 1 + τ 2 +τ 3 ] -1 =[( R eff + R p1 )(C eff,1 +C p1 ) + ( R 2 + R p2 )(C eff,2 +C p2 ) +(g -1 m4 + R p3 )(C eff,3 +C p3 )] -1 (1) where R p and C p stand for parasitic interconnect resistance and capacitance, respectively, R eff is the effective load, seen by the tracking pair, and C eff is the nodal capacitance. These parasitics reduce the pole frequency and as a result degrade the SOF. Moreover, the interlatch feedback can further degrade the SOF by introducing additional phase shift. The layout and interconnect optimization technique is applied to minimize the 1531-1309 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.