IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 30, NO. 3, AUGUST 2017 293 A Testbed for Simulating Semiconductor Supply Chains Hanna Ewen, Lars Mönch, Hans Ehm, Thomas Ponsignon, John W. Fowler, and Lisa Forstner Abstract—In this paper, a supply chain simulation testbed for the semiconductor industry is proposed. We start by identifying requirements for such reference datasets, and then we iden- tify the main building blocks. The nodes of the supply chain that represent semiconductor wafer fabrication facilities (wafer fabs) are built on a simulation model from the measurement and improvement of manufacturing capacity project. We present two techniques to reduce the modeling and computational burden that are able to deal with load-dependent cycle times in single front- end and back-end facilities and in the overall network. The first method models in detail only the bottlenecks in the nodes of the supply chain, while the second one uses empirical distributions for cycle time and throughput. The quality of these reduction techniques is assessed by comparing the detailed model and the models with a reduced level of detail. We present an application scenario for the testbed by simulating a semiconductor supply network. In addition, the usage of the testbed is discussed. Index Terms—Simulation, supply chain management, semicon- ductor manufacturing, testbed, simulation experiments. I. I NTRODUCTION T HE SEMICONDUCTOR industry is characterized by a set of complex manufacturing processes. A semicon- ductor chip is a highly miniaturized, integrated circuit (IC) that consists of thousands of components. Semiconductor manufac- turing starts with wafers, thin discs typically made of silicon. Up to 1000 chips can be produced on each wafer by fabricat- ing the ICs layer by layer in a semiconductor wafer fabrication facility (wafer fab). The corresponding step is referred to as the Fab step. Next, electrical tests that identify individual dice that are likely to fail when packaged are performed in a Probe/Sort facility. An electronic map of the condition of each die is made so that only the good ones are packaged. The wafer fab and the Manuscript received March 20, 2017; revised May 4, 2017; accepted June 1, 2017. Date of publication June 8, 2017; date of current version August 2, 2017. Portions of this paper were presented and published at the 2011 Winter Simulation Conference, Phoenix, AZ, USA, December 2011. (Corresponding author: Lars Möench.) H. Ewen and L. Mönch are with the University of Hagen, 58097 Hagen, Germany (e-mail: hanna.ewen@fernuni-hagen.de; lars.moench@fernuni-hagen.de). H. Ehm, T. Ponsignon, and L. Forstner are with Infineon Technologies AG, 85579 Neubiberg, Germany (e-mail: hans.ehm@infineon.com; thomas.ponsignon@infineon.com; lisa.forstner@infineon.com). J. W. Fowler is with the Department of Supply Chain Management, Arizona State University, Tempe, AZ 85287, USA (e-mail: john.fowler@asu.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TSM.2017.2713775 probe/sort stages are abbreviated by WF/S. The probed wafers are then sent to an Assembly facility where the good dice are put into an appropriate package. Finally, the assembled dice are sent to a Test facility where they are tested to ensure that only good products are sent to customers [1]–[3]. We abbre- viate the assembly and test stages by A/T in the remainder of this paper. WF/S is often called front-end, whereas A/T is called back-end. Note that wafer fab and sort facilities are typically in the same geographic area which is often not the case for A/T. The semiconductor industry is capital intensive which is caused mainly by some extremely expensive machines that cost up to $100 million. The manufacturing process is very complex due to reentrant flows in combination with a large number of unit operations resulting in very long cycle times, a different number of wafers processed at the same time on the various machines, and multiple sources of uncertainty. Capacity expansions are very expensive and time-consuming and must be based on demand forecasts for the next sev- eral years. Because of the rapidly changing environment, the demand is highly volatile. Consequently, the forecast is rarely accurate [4]. Supply chain management (SCM) issues have become more and more important in the last decade. This is due to the global distribution of facilities and the development of various forms of virtual enterprises in the semiconductor industry [5]. Simulation is a well-established method for analyzing both single WF/S and A/T facilities [1]. However, developing a simulation model from scratch is time-consuming and error- prone. Therefore, reference data sets for single wafer fabs [6] are available. Such a data set describes the common ele- ments of an entire class of simulation models. Models that are specific, for instance with respect to the product mix or the dispatching strategy can be constructed based on the reference data set. A testbed contains at least one reference data set. It is ideally formed by several reference data sets that share a common format. The testbed [6] consisting of several simulation reference data sets for single wafer fabs from different semiconductor manufacturers was developed in the MIMAC project [7]. The MIMAC testbed is used by the majority of academic researchers that are involved in model- ing and analysis of semiconductor manufacturing operations. Another, widely used simulation reference data set is the MiniFab model, proposed by researchers at Intel [8]. It is a low complexity simulation model that mimics the typical behavior of a wafer fab by containing the critical elements of a wafer fab including reentrant process flows, batch processing (a batch is 0894-6507 c  2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.