IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 17, NO. 3, MAY/JUNE 2011 671 Device and Integration Technology for Silicon Photonic Transmitters Hyundai Park, Student Member, IEEE, Matthew N. Sysak, Member, IEEE, Hui-Wen Chen, Student Member, IEEE, Alexander W. Fang, Member, IEEE, Di Liang, Member, IEEE, Ling Liao, Brian R. Koch, Senior Member, IEEE, Jock Bovington, Student Member, IEEE, Yongbo Tang, Kristi Wong, Member, IEEE, Matt Jacob-Mitos, Member, IEEE, Richard Jones, Member, IEEE, and John E. Bowers, Fellow, IEEE (Invited Paper) Abstract—The device and integration technology for silicon pho- tonic transmitters are reviewed in this paper. The hybrid silicon platform enables on-chip lasers to be fabricated with silicon pho- tonic circuits and can be integrated in the CMOS back-end flow. Laser arrays from multiple die bonding and quantum well inter- mixing techniques are demonstrated to extend the spectral band- width from the laser array of the transmitter. Two modulator tech- nologies, silicon modulators and hybrid silicon modulators, are also described. Index Terms—Optoelectronic devices, photonic integration, semiconductor lasers, silicon photonics. I. INTRODUCTION O PTICAL data transmission technology is now being con- sidered as a realistic candidate to overcome the bandwidth and distance limitations imposed by the electrical interconnects. The scope of the applications is broad ranging from data centers to the high-bandwidth connectivity of consumer electronics. Today, photonic integration is being driven by the increasing demand of higher data bandwidth with a lower cost. Photonic Manuscript received July 20, 2010; revised October 5, 2010; accepted October 15, 2010. Date of publication March 2, 2011; date of current ver- sion June 8, 2011. This work was supported in part by the Defense Advanced Research Projects Agency and the Applied Research Laboratory under Contract W911NF-05-1-0175, Contract W911NF-04-9-0001, and Contract HR0011-08- 1-0347, in part by Intel, and in part by the HP Innovation Research Program under Contract SBY572738. H. Park, M. N. Sysak, L. Liao, B. R. Koch, and R. Jones are with the Photonics Technology Laboratory, Intel Corporation, Santa Clara, CA 95054 USA (e-mail: hyundai.park@intel.com; matthew.n.sysak@intel.com; ling.liao@intel.com; brian.r.koch@intel.com; richard.jones@intel.com). H.-W. Chen, D. Liang, and J. E. Bowers are with the University of California Santa Barbara, Santa Barbara, CA 93106 USA (e-mail: hwchen@ece.ucsb.edu; dliang@ece.ucsb.edu; bowers@ece.ucsb.edu). A. W. Fang was with the University of California Santa Barbara, Santa Barbara, CA 93106 USA. He is now with Aurrion, LLC, Santa Barbara, CA 93110-1655 USA (e-mail: alexander.fang@aurrion.com). J. Bovington was with the Photonics Technology Laboratory, Intel Corpora- tion, Santa Clara, CA 95054 USA. He is now with the University of California Santa Barbara, Santa Barbara, CA 93106 USA (e-mail: jock@ece.ucsb.edu). Y. Tang is with the Royal Institute of Technology (KTH), Stockholm SE-10044, Sweden, and also with Zhejiang University, Hangzhou 310058, China (e-mail: ytang@ece.ucsb.edu). K. Wong and M. Jacob-Mitos are with Aurrion, LLC, Santa Barbara, CA 93110-1655 USA (e-mail: kristi.wong@aurrion.com; matt.jacob-mitos@ aurrion.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSTQE.2011.2106112 ICs (PICs) offer important gains over discrete components both from technological and economic aspects. Consolidation of in- dividual components on a single chip reduces the coupling loss between elements and minimizes any optical and electrical par- asitic effects leading to improved power efficiency. In addition, for certain applications that require temperature control, the efficiency of the temperature control can be improved as the im- proved power efficiency leads to reduction in power dissipation in PICs. The reduction in chip size also increases the econom- ical advantage of the photonic integration. The manufacturing cost per die greatly depends on the total number of die produced on a single wafer and smaller die size clearly trims off this cost. In addition, the packaging cost is reduced by removing unnec- essary coupling optics for connecting discrete components as well as sharing common packaging elements such as heat sinks (or thermoelectric coolers) and packaging substrate. Improved reliability is another aspect benefited from photonic integration. It has been reported that less frequent fiber-to-chip coupling im- proves the reliability of PICs. Infinera reported over 100 million field hours of 10 × 10 Gb/s transceiver PIC operation without a single failure in service at the end of 2008 [1]. Since the first 10 × 10 Gb/s wavelength division multiplexing (WDM) transceiver in 2004 [2], most of the high-end PICs have been produced on relatively expensive III–V substrates. The industry so far has focused on applications requiring high-end performance where the cost is not the primary driver such as long haul data transmission systems. However, the emerging high-volume low-cost applications require different solutions and scalability. One of the major motivations of silicon photonics is to utilize the existing silicon infrastructure to produce PICs on silicon. Sil- icon manufacturing infrastructure has focused on establishing cost structures suitable for low-cost large-volume applications and its manufacturing technology has been greatly advanced by a large amount of investment over the last decades. The utiliza- tion of existing infrastructure can greatly save the time and cost for optical industry to reduce its cost structure to fulfill the de- mands of low-cost PICs [3]. Typical sizes of silicon substrates are in the range of 200–300 mm diameters that provide at least seven times larger area than InP substrates with 50–75 mm di- ameters. The large size of substrate increases the throughput of the number of die per wafer that, to first order, almost linearly reduces the processing cost per die. In addition, a tight qual- ity control with advanced metrology and testing methodology in manufacturing process can improve the device yield. This 1077-260X/$26.00 © 2011 IEEE