Citation: Mukesh, S.; Zhang, J. A Review of the Gate-All-Around Nanosheet FET Process Opportunities. Electronics 2022, 11, 3589. https://doi.org/10.3390/ electronics11213589 Academic Editors: Yi Zhao and ChoongHyun Lee Received: 3 October 2022 Accepted: 2 November 2022 Published: 3 November 2022 Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affil- iations. Copyright: © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). electronics Article A Review of the Gate-All-Around Nanosheet FET Process Opportunities Sagarika Mukesh †,‡ and Jingyun Zhang * ,‡ IBM Research Albany, Albany, NY 12203, USA * Correspondence: zhangji@us.ibm.com † Current address: 257 Fuller Road, Suite 3100, Albany, NY 12203, USA. ‡ These authors contributed equally to this work. Abstract: In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET are reviewed. These innovations span enablement of multiple threshold voltages and bottom dielectric isolation in addition to impact of channel geometry on the overall device performance. Current scaling challenges for GAA nanosheet FETs are reviewed and discussed. Finally, an analysis of future innovations required to continue scaling nanosheet FETs and future technologies is discussed. Keywords: gate-all-around nanosheet FETs; multi-Vt offerings; bottom dielectric isolation; power- performance improvement; transistor scaling; Moore’s Law 1. Introduction Gate-all-around (GAA) nanosheet field effect transistors (FETs) are an innovative next- generation transistor device that have been widely adopted by the industry to continue logic scaling beyond 5 nm technology node, and beyond FinFETs [1]. Although gate- all-around transistors have been researched for many years, the first performance bench marking on scaled pitch of 44/48 nm CPP (contact-poly-pitch) was presented less than five years ago [2–8]. To fully appreciate the advantages provided by stacked nanosheet gate-all-around transistors, it is important to understand some of the challenges faced by the state-of-the-art FinFETs, and, in general, the trends that have motivated industry wide innovations over the years. Historically, device architecture innovations have been driven by short channel effects (SCEs) that come into play while achieving power performance area (PPA) scaling. SCEs occur when the channel length is on the same order of magnitude as the source-drain depletion layers [9]. Over the years, several innovations, such as the stress technology and high-k metal gate, have enabled scaling [10,11]. FinFETs were the first-ever change in architecture in the history of transistor devices to enable scaling by introducing the trigate control, thereby giving the gate-length scaling another few generations of run- time [12,13]. The gate-all-around nanosheet FETs are only the second time in the history of transistor devices, that a completely different architecture is adopted by the industry. Scaling FinFETs beyond 7 nm node results in exacerbated SCEs, motivating a move from a tri-gate architecture to a gate-all-around architecture [14]. Among the gate-all-around architectures explored by the semiconductor industry, while the nanowires provided best electrostatic control, wider nanosheets are the ones that provide higher “on” current and improved electrostatic control over FinFETs [15,16]. Figure 1 shows a schematic of a FinFET and a GAA nanosheet FET, where the key components of the two technologies are highlighted. The components that are common between the two technologies include the shallow trench isolation, source/drain epitaxies, and the high-k metal gate; whereas the structural differences include a tri-gate for FinFETs vs. gate-all-around for nanosheets. To achieve an advantage in performance, multiple nanosheets must be stacked on top of each other, unlike FinFETs, where one fin constitutes one device. The channel thickness is lithographically defined for FinFETs, which puts a limit on scaling due to patterning Electronics 2022, 11, 3589. https://doi.org/10.3390/electronics11213589 https://www.mdpi.com/journal/electronics