0278-0070 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2015.2474408, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 Abstract—Low power and noise tolerant SRAM cells are in high demand today. This paper presents a stable differential SRAM cell that consumes low power. The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one tail transistor and one complementary word line. Due to stacking effect, the proposed cell achieves lower power dissipation. In this paper, impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional differential 6T (D6T), transmission gate based 8T (TG8T) and single ended 8T (SE8T) SRAM cells. Impact of process variation, like threshold voltage and length, on different design metrics of an SRAM cell like, read static noise margin (RSNM), read access time (T RA ) and write access time (T WA ) are also presented. The proposed cell achieves 1.12×/1.43×/5.62× improvement in T RA compared to TG8T/D6T/SE8T at a penalty of 1.1×/4.88× in T WA compared to D6T/TG8T and 1.19×/1.18× in read/write power consumption compared to D6T. An improvement of 1.12×/2.15× in RSNM is observed compared to D6T/TG8T. The proposed cell consumes 5.38× less power during hold mode and also shows 2.33× narrower spread in hold power @ V DD = 0.4 V compared to D6T SRAM cell. Index Terms— SRAM; low power; RSNM; WSNM; T RA ; T WA ; sensitivity. I. INTRODUCTION TATIC RANDOM ACCESS MEMORYS (SRAMS) are used as cache memory which are embedded in microprocessor, System-on-Chip (SoC), Network-on-Chip (NoC) products. This is due to the fact that they are fast compared to eDRAM (such as DRAM) and main memory (DRAM) [1]. They are fabricated on the same die with processors. As stated by ITRS, 90% of the processor’s chip area is occupied by SRAM [2]. Very high increment in processor’s speed is observed in recent years, but speed of memory has not got such a large increment. Thus, a gap between performing capability of memory and processor is widening with time. To reduce that gap, silicon industry is embedding memory on chip in the form of cache memory. In order to achieve faster cache memory, SRAM cell needs to be faster. For increasing the speed, threshold voltage of MOSFETs needs to be decreased. However, there is a limit up to which threshold voltage can be Manuscript received March 18, 2015; revised June 28, 2015; accepted August 13, 2015. Copyright (c) 2015 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending an email to pubs-permissions@ieee.org. Soumitra Pal, and Aminul Islam are with the Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi, Jharkhand 835215, India (e-mail: soumitra10028.13@bitmesra.ac.in, aminulislam@bitmesra.ac.in). decreased. Furthermore, due to fluctuation in threshold voltage there is a large variation in static noise margin (SNM). Moreover, noise margin is a more critical parameter at the time of read operation than at the time hold operation. SNM is affected by technology and supply voltage scaling [3]. Thus, an SRAM cell is required to be faster and disturb-free during read operation. SRAM cells are used in almost all digital systems and high performance processors. Emerging applications, like wireless body sensing network, bioelectronics and implanted medical instruments demand for power efficient SRAM. Design of a power efficient SRAM cell is one of the most important factors while trying to achieve better chip performances [4]-[7]. More than 40% of the active energy is consumed because of leakage currents in modern high performance processors [8], [9]. An array of SRAM cells is a major source of leakage currents in modern high performance processors because, a large number of transistors are used in today’s on-chip cache memory. Therefore, it is imperative to design a low leakage SRAM cell [3]. By reducing the supply voltage (V DD ), dynamic power decreases quadratically and first order leakage power decreases linearly [10]. Therefore, by operating the cell in subthreshold region (i.e. by lowering the supply voltage below threshold voltage), it is possible to achieve low power SRAM cell [11]-[14]. In deep submicrometer (below 100-nm) technologies, 6T SRAM cell faces many challenges in subthreshold region [15]-[17]. Conventional 6T SRAM cells exhibit poor read stability when operated at low supply voltage [10]. Due to poor read SNM in a 6T SRAM cell, read upset may occur (i.e. data stored in a cell may flip during read operation) [18]. The 6T cell also shows larger variability (less reliable) in submicrometer technology due to variation in process parameters. To overcome the problem of read stability, several SRAM cells are proposed which have some additional supportive peripherals circuits. These cells can be classified into two categories – single-ended SRAM cells [19]-[23] and differential SRAM cells [17], [24]-[25]. Generally, a single ended SRAM cell is not that much robust as a differential one. Therefore, it needs some additional compensation technique to maintain reliability as proposed in [22]. Bit- line leakage in a single ended SRAM cell is data dependent. This is because the overall bit- line leakage depends strongly on the data stored by the cell column being accessed. Therefore, there is a variation in the bit- line leakage from one cell column to another due to which access time distribution for an SRAM cell is highly Soumitra Pal, student Member, IEEE, and Aminul Islam, Senior Member, IEEE Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications S