Optimization of CNOT circuits under topological constraints Bujiao Wu 1,2,3 , Xiaoyu He 1,2 , Shuai Yang 1,2 , Lifu Shou 1,2 , Guojing Tian 1,2 , Jialin Zhang 1,2 , and Xiaoming Sun *1,2 1 Institute of Computing Technology, Chinese Academy of Sciences 2 University of Chinese Academy of Sciences 3 Center on Frontiers of Computing Studies, Department of Computer Science, Peking University December 15, 2021 Abstract CNOT circuit is the key gadget for entangling qubits in quantum computing systems. However, the qubit connectivity of noisy intermediate-scale quantum (NISQ) devices is constrained by their topological structures. To improve the performance of CNOT circuits on NISQ devices, we investigate the optimization of the size/depth of CNOT circuits under topological constraints. We firstly present a method that can optimize the size of any n- qubit CNOT circuit to less than 2n 2 on any connected graph, which is optimal for sparsely connected structures. The simulation experiment shows that our method performs better than state-of-the-art results. Specifically, we present two detailed examples to illustrate the applicability of our algorithm. Furthermore, for the future device with a denser structure, we give a better optimization method that achieves O(n 2 / log δ) size on a graph with the minimum degree δ, which is optimal on the regular graph. Secondly, for the grid structure, which is commonly used in current quantum devices, we demonstrate that the depth of any n-qubit CNOT circuit can be optimized to be linear in n with certain ancillary qubits (ancillas). Our experimental results indicate this method has significant improvements compared with all of the existing methods. We further implement the two circuits commonly used in quantum variational algorithms and quantum chemistry on the 5-qubit IBMQ devices by leverage of our optimization algorithm, the experimental results show the optimized circuit has far less error when there exists noise compared to IBM mapping method. 1 Introduction Quantum circuit synthesis is a process to construct a quantum circuit that implements a desired unitary operator and optimizes its size/depth in terms of a given gate set, which is an important task in the field of quantum computation and quantum information [1, 2, 3]. There are two key limitations of the current intermediate-scale quantum devices. First, the performance and reliability of quantum devices heavily depend on the length of time that the underlying quantum states can remain coherent. Hence it is natural to design * Email address: sunxiaoming@ict.ac.cn 1 arXiv:1910.14478v3 [quant-ph] 17 Aug 2021