Advanced rail clamp networks for ESD protection Michael Stockinger * , James W. Miller, Michael G. Khazhinsky, Cynthia A. Torres, James C. Weldon, Bryan D. Preble, Martin J. Bayer, Matthew Akers, Vishnu G. Kamat 1 Motorola, 3501 Ed Bluestein Blvd., Austin TX 78721, USA Received 11 December 2003; received in revised form 22 March 2004 Available online 8 July 2004 Abstract A new, area efficient, boosted and distributed active MOSFET rail clamp network for I/O pad ESD protection is presented. In addition, a compact new rail clamp trigger circuit with high resistance to false triggering is introduced. Ó 2004 Elsevier Ltd. All rights reserved. 1. Introduction Increasingly prevalent in advanced CMOS integrated circuits, networks of active MOSFET rail clamps have proven to offer robust, scalable, portable and easily simulated I/O pad ESD protection [1–8]. It has previ- ously been shown in [6] by the authors that highly effi- cient ESD protection networks can be built by distributing RC triggered active MOSFET clamps, wired in parallel, in each I/O and power supply pad cell around the perimeter of an integrated circuit and guidelines were given for accurate SPICE simulation of these ESD networks and procedures for using these simulations to optimally size key ESD elements to just meet the required ESD performance, while minimizing layout area. Now we extend the framework presented in [6] by introducing four significant improvements. First we present a new ‘‘boosted’’ RC triggered ESD rail clamp circuit configuration, wherein the rail clamp NMOS gate is boosted to a voltage higher than the device drain during an ESD event. Compared to prior approaches, this boosted configuration allows for an up to 2.3 times reduction in the clamp NMOS width and layout area, while still retaining comparable ESD pro- tection. In addition, when implemented in a distributed rail clamp network, the boosted approach enables the effective use of remote rail clamp trigger circuits, thereby eliminating the need for a trigger circuit local to the clamp NMOS in each I/O pad cell. This further reduces layout area. Second, we introduce a more comprehensive distrib- uted ESD network optimization strategy which allows for precise sizing of the high-current ESD elements in the I/O pad cell. In our optimizations, we size the ESD elements to move the required ESD current and protect both the fragile NMOS and PMOS output buffers for all worst case zap conditions, while occupying an absolute minimum combined layout area. Third, we further extend the distributed clamp idea presented in [6] to its ultimate embodiment. Whereas in [6] distributed networks were formed from discrete clamps placed in each I/O and power supply pad cell, here we introduce a new approach where clamp NMOS devices are continuously distributed along the IC periphery included not only in pad cells, but also be- tween pad cells to fill any gaps in the continuous dis- tributed network. We will show that this further reduces ESD layout area and increases design modularity. Fourth, we introduce a new robust and compact slew rate sensing trigger circuit for active MOSFET ESD rail clamps, which is significantly superior to prior circuits in * Corresponding author. Tel.: +1-512-933-6016. E-mail address: m.stockinger@motorola.com (M. Stockin- ger). 1 Synopsis Inc., 700 E. Middlefield Road, Mountain View, CA 94043, USA. 0026-2714/$ - see front matter Ó 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2004.05.009 Microelectronics Reliability 45 (2005) 211–222 www.elsevier.com/locate/microrel