Low-voltage power-efficient adaptive biasing for CMOS amplifiers and buffers S. Baswa, A.J. Lo ´pez-Martı ´n, R.G. Carvajal and J. Ramı ´rez-Angulo Novel adaptive biasing techniques, suited for low-voltage operation, are presented. They provide small and accurately controlled quiescent currents, which are automatically boosted when an input signal is applied. Measurement results of an OTA using these techniques and fabricated in a 0.5 mm CMOS technology show a slew rate of more than 40 V=ms for an 80 pF load capacitance and a static power consumption of only 140 mW. Introduction: Proliferation of battery-operated systems has given rise to an increased demand for low-voltage low-power circuits, in the search for less weight and size and extended operative lifetime of the batteries. In this context, it is critical to preserve the dynamic performance of analogue circuits with both minimum supply voltage and minimum standby power consumption. Adaptive (or dynamic) biasing circuits [1] are very useful in this context. They provide a variable bias current only in the presence of an input signal. In the absence of such input, they provide a constant quiescent current, which can be accurately controlled. This way, static power consump- tion is reduced without compromising the transient behaviour. These circuits are widely employed in class-AB opamps, and several proposals are available [1]. However, most of them fail to operate at low supply voltage and=or with large boosting of the bias current under dynamic conditions. In this Letter we propose new adaptive biasing topologies that feature favourable performance in terms of quiescent and dynamic characteristics, and which are able to operate with minimum supply voltage V DD MIN ¼jV GS jþ2jV DSsat j, where jV DSsat j is the minimum jV DS j to keep the transistor in saturation. Fig. 1 Adaptive biasing of PMOS differential pair Adaptive biasing of input stages: To illustrate the proposed techni- que, it will be applied to the design of power efficient differential input stages (Fig. 1). In modern applications very stringent requirements are imposed to the adaptive biasing block of Fig. 1, among them (i) ability to set low and accurately controlled quiescent currents; (ii) very low output resistance and large sourcing capability, as the common source of M 1 and M 2 is a low impedance node; (iii) large peak output currents in order not to limit settling by slew rate; (iv) low voltage operation; (v) reduced number of transistors due to noise, bandwidth and silicon area considerations. Proposed adaptive biasing circuits: To meet these requirements, we propose the adaptive biasing technique shown in Fig. 2a. The goal is to set an accurately controlled voltage V CMS at the common source node of M 1 and M 2 in Fig. 1. This voltage should be able to track the common mode input voltage, so it can be expressed as V CMS ¼ V CM þ V B . Voltage V CM is the input common mode voltage, i.e. V CM ¼ (V INP þ V INM )=2, and V B is a constant DC level shift. From Figs. 1b and 2a, it can be noticed that, when V INP ¼ V INM ¼ V CM , i.e. under quiescent conditions, the adaptive biasing block forces V SG1 Q ¼ V SG2 Q ¼ V B . Therefore, quiescent current through M 1 and M 2 is accurately set by V B and do not depend on V CM . Choosing V B slightly larger than jV TH j very low quiescent current can be achieved. However, when a differential input voltage is applied, an unbalance in V SG1 and V SG2 is produced which leads to different currents in M 1 and M 2 the maximum value of which is not limited by the quiescent current. Note that under dynamic conditions operation is also inde- pendent of V CM , and a large CMRR can be obtained. To generate the voltage V CMS , a common mode sensing (CMS) circuit is required, as shown in Fig. 2a. Such a CMS circuit should have very high input impedance, in order not to load the inputs. In addition, it should be fast, simple, and able to operate at low supply voltages with low power consumption. Moreover, as shown in Fig. 2a,a buffer is required in order not to load the CMS circuit and to provide enough current sourcing capability. This buffer should feature accurate voltage copy, high input resistance, very low output resistance, simpli- city, as well as low voltage and low power requirements. Fig. 2 Diagram of adaptive biasing circuit, proposed common mode sensing circuit, buffer employing FVF, buffer using feedback amplifier a Diagram of adaptive biasing circuit b Proposed common mode sensing circuit c Buffer employing FVF d Buffer using feedback amplifier CMS circuit: Fig. 2b shows a new CMS circuit that fulfils the aforementioned requirements. To provide high input resistance and to up-shift the input voltage, two simple and very efficient level shifter buffers, that we coined as ‘flipped voltage followers’ (FVFs) [2], are employed. One of them corresponds to M 3 , M 5 and the left current source I B , and the other to M 4 , M 6 and the right current source I B . Since the drain current of matched transistors M 3 and M 4 is constant, neglecting second order effects a constant DC level shift is applied to the inputs, equal to V SG3,4 Q and thus dependent on I B . Note that if conventional source followers were employed, input variations would lead to different drain currents in the source follower transistors, and therefore to non-symmetrical DC level shifts. Voltages at nodes N 1 and N 2 will be V INP þ V SG3,4 Q and V INN þ V SG3,4 Q , respectively. Assum- ing that R 1 ¼ R 2 , voltage at node N C will be V CMS ¼ (V INP þ V INM )=2 þ V SG3,4 Q ¼ V CM þ V SG3,4 Q . If this voltage is applied to the common source terminal in Fig. 1b, under quiescent conditions V SG1 Q ¼ V SG2 Q ¼ V B ¼ V SG3,4 Q , so assuming that M 1 M 2 , M 3 and M 4 are matched, quiescent current in the differential pair is I B , and can thus be adjusted by the current sources of the CMS circuit. Buffer circuit: Figs. 2c and d show two topologies that we propose for the implementation of the buffer in Fig. 2a. The first one, shown in Fig. 2c, consists basically on an FVF, formed by transistors M 9 and M 12 , and a level shifter. The FVF cell has all the aforemen- tioned desirable features, such as a very low output resistance and large current sourcing capability. However the FVF output is up- shifted with regard to the input, and therefore an identical input down-shifting is required. This is achieved by transistor M 8 (matched with M 7 , M 9 ) acting as source follower. It also biases ELECTRONICS LETTERS 19th February 2004 Vol. 40 No. 4