IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 51, NO. 5, MAY 2004 257 New Compact CMOS Continuous-Time Low-Voltage Analog Rank-Order Filter Architecture Jaime Ramírez-Angulo, Fellow, IEEE, Ramon Gonzalez-Carvajal, Member, IEEE, Gladys Omayra Ducoudray, Antonio J. López-Martín, Member, IEEE, and Antonio Torralba, Senior Member, IEEE Abstract—A new compact CMOS continuous-time analog rank- order filter topology is presented. The hardware complexity grows linearly with the number of inputs at the rate of only two transis- tors per input. The implementation is based on a multiple input differential structure. The rank is programmable with the tail cur- rent source for all rank-order values from the Min to the Max case. The circuit has low voltage and low power consumption require- ments. Experimental results are presented that verify the function- ality and accuracy of the circuit. Simulation results show satisfac- tory operation in the 100-MHz frequency range for 0.5- m CMOS technology and using a single 1.8-V supply. Two buffered versions of the circuit and efficient techniques for reduction of corner er- rors are also discussed. Index Terms—CMOS analog circuits, low-voltage analog circuits, median filter, minimum circuit, rank-order filter, trans- conductance comparator, winner-take-all circuit. I. INTRODUCTION H IGH-SPEED analog rank-order filters (ROFs) can find application in real-time image and speech pro- cessing, data compression, communications, neural and fuzzy networks, etc. For an -input ROF filter, the output signal is the th rank-order signal, defined as the th input signal in increasing order of amplitude. The Min case corresponds to , the Max case to , and the Median case to . Three basic approaches have been proposed for implementation of analog ROFs. 1) Feedforward systems based on multistage sorting Min and Max circuits that arrange signals in increasing order of amplitude [1]–[3]. In this approach, the number of stages and hardware complexity increases rapidly with the number of input signals. 2) Continuous-time negative feedback approaches based on transconductance comparators with symmetrical output current saturation characteristics [4], [5]. This approach provides the th rank-order signal in just one step, and hardware complexity grows only linearly with the number of inputs . Manuscript received January 12, 2002; revised November 3, 2003. This paper was recommended by Associate Editor J. Silva Martinez. J. Ramírez-Angulo and G. O. Ducoudray are with the Klipsch School of Elec- trical and Computer Engineering, New Mexico State University, Las Cruces, NM 88003 USA (e-mail: jramirez@nmsu.edu). R. Gonzalez-Carvajal and A. Torralba are with the Escuela Superior de In- genieros, Universidad de Sevilla, E-41092 Seville, Spain (e-mail: carvajal@ gtex10.us.es). A. J. López-Martín is with the Department of Electrical and Electronic Engineering, Public University of Navarra, E-31006 Pamplona, Spain (e-mail: antonio.lopez@unavarra.es). Digital Object Identifier 10.1109/TCSII.2004.827553 3) Sample data approaches based on capacitive threshold logic [6], [7]. The hardware complexity of this approach grows also rapidly with , and it has an inherent speed limitation due to sample data operation. The approach of [4] and [5] is the least hardware intensive among previously reported analog rank extractors and has potential for very high-speed operation. It uses transconduc- tance comparators connected in voltage follower configuration (Fig. 1). All transconductor outputs are connected to a common output node and the rank order is easily selected in terms of the value of a dc current source injected at the output node. Hardware complexity grows linearly with the number of inputs at the rate of one transconductance comparator (ten transistors in [5]) per input. In this paper, a more compact CMOS implementation of a continuous-time analog ROF is presented. In this implementa- tion described in Section II, hardware complexity grows also linearly with the number of inputs, but at the rate of only two transistors per input. It is based on a multiple input differen- tial structure and requires, in its basic form, only two transistors per input. Rank is easily programmed using the biasing tail cur- rent source for all values from (Min case) to (Max case). Besides its simplicity, the im- plementation proposed here can operate at high frequency with low supply voltage and very low power consumption. Output buffered versions and efficient techniques for corner error re- duction are discussed in Section III. Experimental and simula- tions results that verify the circuit functionality and potential for high-frequency operation are included in Section IV. Finally, in Section V the main conclusions of this work are drawn. II. NEW COMPACT CMOS ANALOG ROF The basic scheme of the proposed rank-order circuit is shown in Fig. 2(a). It consists of a differential amplifier structure with input branches and an output branch biased with a dc cur- rent . A tail current source with programmable values is used. The index determines the rank order of the filter and can take values in the range (i.e., ). Each th branch includes an nMOS tran- sistor and a pMOS transistor . The gate of the nMOS transistor is connected to an input signal . The gate of the pMOS transistor is connected to a common biasing voltage . pMOS transistors in the input branches can operate either in cutoff mode or in saturation mode. In the latter case, operates as a current source and delivers a current to the corresponding nMOS transistor . The output branch in- cludes a diode-connected nMOS transistor (identical to 1057-7130/04$20.00 © 2004 IEEE