978-1-4799-2079-2/13/$31.00 ©2013 IEEE FPGA-Based Reconfigurable Unit for Image Filtering in Frequency Domain Luis M. Ledesma-Carrillo, Misael Lopez-Ramirez, Ana L. Martinez-Herrera, Eduardo Cabal-Yepez, Arturo Garcia-Perez. Division de Ingenierias, Campus Irapuato-Salamanca, Universidad de Guanajuato / Carr. Salamanca-Valle km 3.5+1.8, Comunidad de Palo Blanco, 36700 Salamanca, Guanajuato, Mexico. {e.cabal-yepez@gmail.com} Abstract— Digital filtering is a key step of image processing in many applications. Due to its importance in this work a general FPGA-based reconfigurable architecture for real-time, online image filtering in the frequency domain is presented. The proposed FPGA-based implementation is portable to distinct platforms from different vendors. Obtained results from different study cases show the high capability and performance of the proposed hardware implementation by applying any user designed filtering operation on an image, and outperforming by two orders of magnitude its software implementation counterpart. Keywords- 2D-FFT; Frequency domain; FPGA; Generic architecture; Image filtering; Real-time image processing. I. INTRODUCTION The two-dimensional Fast Fourier transform (2D-FFT) and its inverse (2D-IFFT) play an important role in digital image processing to provide filtering solutions for many applications as robotics, optics, telecommunications, and bio-imaging, among others. Nowadays, filtering is utilized for image processing operations like denoising, edge detection, recognition, segmentation, smoothing, and restoration [1], [2]. For instance, in [3], meteorological images are filtered utilizing the Fourier transform to predict storms by analyzing the frequency contents in an image taken by a satellite. In [4], different types of digital filters namely average filter, median filter, and wiener filter are described and compared for removing noise present in transmission electron microscopy images of nanomaterials. In [5], a method based on median filtering to compute the total variation with respect to the central pixel in a filter window is introduced to detect edges of nuclei in microscopy images. In [6] different low-pass filtering schemes are applied to restore a gray scale image corrupted by Salt & Pepper noise. The efficiency of each filtering scheme is evaluated through mean square error, signal to noise ratio, peak signal to noise ratio and signal to noise ratio improvement. In [7], a filter-learning model is built based on the theory of function approximation and the generalization of the partial differential equation model for image deblurring. From here, it is clear that digital filtering is a key step of image processing in many applications. Due to its importance for image processing, different implementations have been proposed to compute the 2D-FFT in hardware. For instance, in [8], a 4096-point radix-8 fast Fourier transform (FFT) is designed and implemented on a field programming gate array (FPGA). The proposed architecture utilizes a pipeline structure to process 4096 point in 20.48 µs at 100 MHz. In [9], a complex, single precision, floating-point, one-dimensional fast Fourier transform (1D- FFT) implementation is proposed and compared in performance against graphic processing unit (GPU) accelerators. In [10], an implementation of Laplacian sharpening and 2D-FFT transform in an FPGA is used to assess the quality of the iris image in a Texas Instrument digital signal processor (DSP) based iris recognition system. In [11], a real-time, embedded automated image recognition system is introduced utilizing a combination of a DSP to implementing the distance-classifier correlation filter algorithm, and an FPGA to implement computational bottlenecks like the 2D-FFT and 2D-IFFT operations. In [12], a High Level framework for the implementation of FFT in an FPGA for real-time image processing applications is presented. The proposed architecture is implemented in two Celoxica-Rc1000 development boards utilizing the hardware description language (HDL) Handel-C. In [13], the design and realization of a high level Handel-C based framework, which includes wide range of FFT algorithms like radix-2, radix-4, split-radix, and fast Hartley transform, for the implementation of 1D and 2D FFTs in image filtering applications is reported. In [14], a stream, coarse grained, and application-specific pipeline architecture described in data flow graph (DFG) is proposed for accelerating 2D-FFT computation in embedded and multimedia applications. A major disadvantage of the methods described above is their lack of portability among different FPGA platforms, in part due to the utilization of object orient programming (OOP) languages like Handel-C or DFG during their description. Another disadvantage of utilizing OOP languages for hardware description is that they do not guarantee optimal resource utilization in the FPGA device since they are not proper hardware description languages, but programming languages that allow expressing algorithms without worrying too much about in how the underlying computation engine works [15]. The contribution of this work is the development of a generic, FPGA-based, reconfigurable architecture for online image filtering in the frequency domain, in real-time. The proposed generic architecture implements the 2D-FFT and the 2D-IFFT in hardware utilizing very high speed integrated circuits hardware description language (VHDL). Different from previous approaches, the generic VHDL-based hardware description allows portability to different FPGA platforms for image filtering in distinct applications. To assess the performance and effectiveness of the proposed generic hardware architecture, five different study cases in