IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 26, NO. 3, AUGUST 2013 361 Manufacturing Challenges of GaN-on-Si HEMTs in a 200 mm CMOS Fab D. Marcon, B. De Jaeger, S. Halder, N. Vranckx, G. Mannaert, M. Van Hove, and S. Decoutere Abstract —In this paper, we report on the challenges related to growth and processing of 200 mm GaN-on-Si wafers in a CMOS fab. We describe the Au free process we developed as well as how we assure wafer quality prior processing. For the first time, we analyze possible Ga contamination issues related to the processing of GaN wafers and we present the cleaning procedures we developed to avoid it. Index Terms—Contamination, Gallium nitride, processing, power semiconductor devices, semiconductor device manufac- ture. I. Introduction P OWER SWITCHING devices are daily present in our life. For instance, they convert the high voltage coming from the grid to the low voltage needed on our computers. Nowadays, this conversion is not performed efficiently and therefore energy is just wasted as heat. This is because the power switching devices of today are based on Si-technology that has reached its limits in terms of efficiency and operating frequency. Gallium nitride (GaN) and Silicon Carbide (SiC) tech- nologies are the most promising candidates for performance beyond the Si limits. Compared to SiC, which is available only as small diameter and expensive wafers, GaN combines high performance with a low cost technology thanks to the fact that GaN can be grown on 200 mm inexpensive Si(111) substrates (GaN-on-Si) [1] that can be processed in a high productivity CMOS fabrication plant (fab). In this work, we analyze the challenges and possible issues related to the manufacturing of 200 mm GaN-on-Si wafers in a CMOS fab. II. Fundamentals of the GaN Technology A typical epistack for GaN technology consists of a thick Al(Ga)N-based buffer layer that is epitaxially grown on a foreign substrate such as Si, SiC or Sapphire. This is followed by a GaN channel layer on which a thin AlGaN barrier layer is grown. The interaction between the latter two materials Manuscript received February 15, 2013; revised March 18, 2013; accepted March 25, 2013. Date of publication March 29, 2013; date of current version July 31, 2013. This paper was recommended by Associate Editor H. Koike. D. Marcon, B. De Jaeger, S. Halder, N. Vranckx, G. Mannaert, M. Van Hove and S. Decoutere are with imec, kapeldreef 75, B-3001. Leuven, Belgium. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TSM.2013.2255897 Fig. 1. TEM image of the full GaN-on-Si epitaxial stack. The upper part, i.e., active region of the stack is magnified in the inset. gives rise to the spontaneous formation of a two dimen- sional electron gas (2DEG), which is well confined at the AlGaN/GaN interface thanks to the difference in bandgap of the two materials [2]. Since the 2DEG is spontaneously formed without any doping, electrons in the 2DEG have high mobility. By defining a metal gate in between two ohmic contacts i.e. source and drain, it is possible to modulate the flow of electrons from one contact to the other via the 2DEG, resulting in a high electron mobility transistor (HEMT). III. Gan-on-Si Epitaxy Due to the large lattice mismatch between (Al)GaN and Si, growing high quality crack-free GaN epitaxial layer on 200 mm Si substrates has required an intensive optimization of the epitaxy [1]. The main challenge at the epitaxial level is to obtain a high and uniform epitaxial quality combined with a sufficiently low wafer bow to allow processing in a CMOS fab. The wafer bow has been successfully controlled below ±50 μm by using stress mitigating buffer layers as well as 1.15 mm thick Si substrates instead of the standard 0.725 mm thick substrates. Currently, we are working towards an epitaxial technology that utilizes Si substrates with standard thickness. More details on the GaN- on-Si epitaxy can be found elsewhere [1]. 0894-6507/$31.00 c  2013 IEEE