Scaling down the interpoly dielectric for next generation Flash memory: Challenges and opportunities B. Govoreanu a, * , D.P. Brunco b , J. Van Houdt a a IMEC Leuven, Kapeldreef 75, B-3001 Leuven, Belgium b Intel Corp. c/o IMEC, Kapeldreef 75, B-3001 Leuven, Belgium Available online 8 November 2005 The review of this paper was arranged by E. Gerritsen, P. Masson and P. Mazoyer Abstract We review the main issues in scaling down the interpoly dielectric (IPD) for future floating gate Flash memory technology genera- tions. The equivalent oxide thickness (EOT) of the IPD must reach the sub-10 nm range to enable lowering of the operating voltages and further scale device feature sizes. Additionally, the loss of control gate wrap around the floating gate for high density memories as device dimensions scale down will require a drastic reduction (up to 60%) in IPD EOT to maintain the same capacitive coupling. As the scalability of the conventional oxide-nitride-oxide (ONO) IPDÕs is limited, we propose new solutions that exploit the opportunities offered by the high-j dielectrics. Their effectiveness increases when midgap and p-type metals are considered, instead of the conventional polysilicon control gate. The optimal approach depends on the most critical requirement that the IPD has to fulfill, which in turn is appli- cation or device-structure dependent. The nonideal nature of the dielectric materials, however, may severely reduce the design window, calling for a sustained effort to improve their electrical properties by process optimization. Ó 2005 Elsevier Ltd. All rights reserved. Keywords: Flash memory; Floating gate; Interpoly dielectrics; Scaling; High-j materials; Reverse-VARIOT; Metal gate 1. Introduction Scaling of the conventional tunnel oxide for Flash mem- ory technology is close to its limits. Research is needed to circumvent this lack of scalability, and thus to allow the voltages to scale down and keep pace with mainstream CMOS technology. On a longer term, revolutionary research [1] may lead to entirely new nonvolatile memory (NVM) devices. In the near future, evolutionary research will presumably maintain the ‘‘template’’ of the existing memory devices, e.g., floating gate device structures, and seek to improve the elements responsible for charge trans- port on both a short time scale (for programming and eras- ing), as well as on a long time scale (for retention). Hence, a possible route is to research novel tunnel barriers and inter- poly dielectrics (IPDÕs) that are able to meet the perfor- mance requirements of Flash memory. Although the successful implementation of a memory concept will ulti- mately be dictated by cost, a thorough investigation is needed to explore their capabilities and limits. In this work, we focus on the scalability of the IPDÕs in the sub-10 nm range. 2. Interpoly dielectric requirements Good IPDÕs must fulfill several conditions. First, to allow fast enough operation of the device they must be elec- trically thin enough to ensure good electrical coupling to an external electrode, commonly referred to as the control gate (CG). This allows for a significant part of the voltage applied over the entire stacked gate structure to be trans- ferred to the tunnel dielectric. However, too strong a cou- pling will actually decrease the V T shift corresponding to a 0038-1101/$ - see front matter Ó 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2005.10.018 * Corresponding author. Tel.: +32 16 281 337; fax: +32 16 281 844. E-mail address: govorean@imec.be (B. Govoreanu). www.elsevier.com/locate/sse Solid-State Electronics 49 (2005) 1841–1848