Received: 25 May 2020 - Revised: 17 March 2021 - Accepted: 19 March 2021 - IET Circuits, Devices & Systems DOI: 10.1049/cds2.12074 ORIGINAL RESEARCH PAPER FPGACam: A FPGA based effcient camera interfacing architecture for real time video processing Sayantam Sarkar 1 | Satish S. Bhairannawar 2 | Raja K.B. 3 1 Department of Electronics and Communication Engineering, Vijaya Vittala Institute of Technology, Bangalore, Karnataka, India 2 Department of Electronics and Communication Engineering, Shri Dharmasthala Manjunatheshwara College of Engineering and Technology, Dharwad, Karnataka, India 3 Department of Electronics and Communication Engineering, University Visvesvaraya College of Engineering, Bangalore, Karnataka, India Correspondence Sayantam Sarkar, Department of Electronics and Communication Engineering, Vijaya Vittala Institute of Technology, Bangalore, Karnataka‐560077, India. Email: sayantam.61@gmail.com Abstract In most of the real time video processing applications, cameras are used to capture live video with embedded systems/Field Programmable Gate Arrays (FPGAs) to process and convert it into the suitable format supported by display devices. In such cases, the interface between the camera and display device plays a vital role with respect to the quality of the captured and displayed video, respectively. In this paper, we propose an effcient FPGA‐based low cost Complementary Metal Oxide Semiconductor (CMOS) camera interfacing architecture for live video streaming and processing applications. The novelty of our work is the design of optimised architectures for Controllers, Converters, and several interfacing blocks to extract and process the video frames in real time eff- ciently. The fexibility of parallelism has been exploited in the design for Image Capture and Video Graphics Array (VGA) Generator blocks. The Display Data Channel Conversion block required for VGA to High Definition Multimedia Interface Con- version has been modifed to suit our objective by using optimised Finite State Machine and Transition Minimiszed Differential Signalling Encoder through the use of simple logic architectures, respectively. The hardware utilization of the entire architecture is compared with the existing one which shows that the proposed architecture requires nearly 44% less hardware resources than the existing one. 1 | INTRODUCTION Vision is one of the most prominent senses present in the humans [1] due to which real time vision based system or a part of the system are commonly used in various real‐time applica- tions. In general, any real time video/image processing tech- nique can be split into four main processing blocks, namely Sensor, Memory, Processing Unit, and Display [1, 2]. (i). Sensor: It is used to capture video sequences from the external envi- ronment and transform it into corresponding electrical signals suitable for further processing. (ii). Memory: It is internal RAM where the captured video sequences are stored temporarily for further processing. This block also helps to synchronize data between the sensor and processing unit where both the blocks are operated at different frequencies. (iii). Processing Unit: In this section, the required processing algorithm/architecture is implemented. This block accepts data from Memory. (iv). Display: This block accepts the processed data and converts it into the required format supported by the display device. In this paper, we propose a new Very Large Scale Integrated Circuit architecture to interface low cost Complementary Metal Oxide Semiconductor (CMOS) camera and display device with processing elements to FPGA board effciently and also to display the video directly using a display device, such as monitor or TV. The entire architecture is optimised to get lower hardware utilizations without affecting the architectural accuracy which is implemented using Vivado 2018.3 tool where the coding is performed by using the standard Very High‐Speed Integrated Circuit Hardware Description Language (VHDL) language [3]. This architecture is synthesized and tested in real time using Digilent NexysVideo (xc7a200t-1sbg484c) FPGA board [4] and Zybo Z7-10 (xc7z010-1clg400c) FPGA Board [5] separately where NexysVideo is of a medium level FPGA and Zybo Z7‐10 is of a low level FPGA. The level of FPGA is generally defned This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. © 2021 The Authors. IET Circuits, Devices & Systems published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology. IET Circuits Devices Syst. 2021;1–16. wileyonlinelibrary.com/journal/cds2 - 1