Carrier charging effect of V 3 Si nanocrystals floating gate memory structure Dongwook Kim, Dong Uk Lee, Hyo Jun Lee, Eun Kyu Kim ⁎ Quantum-Function Research Laboratory and Department of Physics, Hanyang University, Seoul 133-791, South Korea abstract article info Available online 15 February 2012 Keywords: Nanocrystals V 3 Si Nonvolatile memory Tunnel layer Thermal annealing We fabricated V 3 Si nanocrystals embedded in SiO 2 dielectric layer as a function of post- annealing conditions and characterized their charging effect to apply a nonvolatile memory device. The V 3 Si thin layer of 5-nm-thickness was deposited on the SiO 2 tunneling layer by r.f. sputtering system. To create nanocrystals structure, the post- annealing process in N 2 gas ambient by rapid thermal annealing method was done at temperature ranges from 600 °C to 1000 °C as a function of annealing times. After the post-annealing at 800 °C for 5 s, the spherical shaped V 3 Si nanocrystals with average diameter of 4 nm were formed. From the nano-floating gate capacitor structure with V 3 Si nanocrystals, the memory window was measured about 3.4 V when the sweeping voltages applied from -9 V to 9 V and from 9 V to -9 V. This result indicates that V 3 Si nanocrystals have a strong potential for the nonvolatile memory device. © 2012 Elsevier B.V. All rights reserved. 1. Introduction The nano-floating gated flash memories make possible smaller oxide thickness and smaller operating voltage. The charge storage into nanocrystals of floating gate has fast write times due to direct tunneling through the thin tunnel oxides. Non-volatility and longer retention time are possible at smaller electron injection in thin tunneling oxide than other flash memory system. The electrons injected into two-dimensionally confined nanocrystal through a very thin oxide by direct tunneling, and then the single-electron and confinement effects in electron storage saturate the nanocrystals memory. Because the energy levels in nanocrystal describe by a quan- tum mechanical mean-field potential, the quantum states in nanopar- ticles are quite different from those of metallic states. Nanocrystals have a potential well, which attributed to the difference in the work functions between nanocrystals and oxide layer [1–6]. The vanadium silicide (V 3 Si) with a bcc structure has the work function of 4.63 eV and high-temperature stability and good electrical properties. So, it is widely used in microelectronics to produce Ohmic and rectifying contacts, gates, conducting lines and other elements [7]. The V 3 Si is a member of the cubic A-15 structure class under stan- dard conditions and undergoes a transformation to tetragonal struc- ture below T c of 17 K. Then, superconductivity below T c has been reported for tetragonal V 3 Si [8–11]. The vanadium has one of the low- est interstitial diffusion coefficients of all 3 d metal in intrinsic silicon crystals, and then its diffusivity has reported from 1.8 × 10 -8 cm/s to 3.4 × 10 -11 cm/s at 1100 °C. Therefore, the V 3 Si nanocrystals can be improved the electrical properties of nonvolatile memory device by work function difference to that of SiO 2 dielectrics. In this study, we fabricated the V 3 Si nanocrystals embedded in SiO 2 dielectrics layer as function of post-annealing conditions to V 3 Si thin film. In the nano-floating gate capacitor with V 3 Si nanocrys- tals, the memory charging effect was analyzed by capacitor–voltage (C–V) measurement. A focused ion beam situ etching method was used to prepare the cross-sectional transmission electron microscopy sample. The morphology of V 3 Si nanocrystals was analyzed by a FEI Tecnai G2 F30 field-emission transmission electron microscopy (FE- TEM) operated at 300 kV. We discussed a feasibility of V 3 Si nanocrys- tals to apply a nonvolatile memory device. 2. Experiment We have studied the formation of V 3 Si nanocrystals on SiO 2 surface by using deposition of vanadium silicide thin film and post thermal anneal- ing processes. After cleaning of p-type Si wafers, the 5-nm-thick SiO 2 tunneling layer was grown by dry oxidation at 1000 °C for 30 min under O 2 ambient. Then, the V 3 Si thin layer (5 nm) was deposited on this tunneling layer by r.f. sputtering system. To create the nanocrystals structure, the first post-annealing process in N 2 gas ambient by rapid thermal annealing method was done at temperatures of 600 °C, 700 °C, 800 °C, 900 °C and 1000 °C as a function of annealing times. Then, the 20-nm-thick control SiO 2 layer was deposited by ultra-high vacuum sput- ter. Finally, the metal-oxide-semiconductor (MOS) structure with V 3 Si nanocrystals was formed by defining of an Al metal gate on the top of the SiO 2 control dielectric layer. The schematic of cross-sectional struc- ture of the V 3 Si nanocrystal floating gate memory was shown in Fig. 1. This structure is the nanocrystals gated capacitor for non-volatile memory device. To prepare the FE-TEM samples of MOS device with V 3 Si nano- crystals, the focused ion beam milling was carried out with a FEI Quanta Thin Solid Films 521 (2012) 94–97 ⁎ Corresponding author. Tel.: + 82 2 2295 0914; fax: + 82 2 2295 6868. E-mail address: ek-kim@hanyang.ac.kr (E.K. Kim). 0040-6090/$ – see front matter © 2012 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2012.02.045 Contents lists available at SciVerse ScienceDirect Thin Solid Films journal homepage: www.elsevier.com/locate/tsf