A 1.8 V low power 5 Gbps PMOS-based LVDS output driver with good return loss performance Hazem W. Marar • Khaldoon Abugharbieh • Abdel-Karim Al-Tamimi Received: 23 July 2013 / Revised: 25 October 2013 / Accepted: 3 November 2013 / Published online: 19 November 2013 Ó Springer Science+Business Media New York 2013 Abstract This paper presents a novel design topology of a 5 Gbps PMOS-based low voltage differential signaling (LVDS) voltage mode output driver. The topology is designed to meet the requirements of low power con- sumption and high data rates applications. The driver consists of an output stage and a pre-driver stage where the driver’s swing and common-mode output voltage are set. The pre-driver and the output stage consume only 13.1 mW of power at 5 Gbps speed while operating from a 1.8 V voltage supply. Further, the design achieved -21 dB return loss performance at DC. The driver was extracted and simulated using Mentor Graphics CAD tools and implemented in 180 nm CMOS technology. The output signal is fully compliant with the LVDS standard output swing and common-mode voltage specifications. Keywords Low-voltage-differential-signaling (LVDS)  Low power  Transmit driver  High speed 1 Introduction With the recent rapid increase in high-speed applications and the ever-increasing performance demands on commu- nication systems, higher data rates and processing speeds are required. In the past, high-speed transmission was achieved by parallel processing and pipelining. However, with the increasing challenges related to the complexity and cost for the IC packaging and the printed circuit boards fabrication, design engineers are required to focus on enhancing the performance of serial signal transmission. Nevertheless, as the speed of data transmission increases, challenges related to signal integrity and power consump- tion become more significant. When transmitting data at high speed along a communication channel, the signal will suffer from attenuation and reflection. Therefore, the bit error rate of the system may increase to un-acceptable levels. To overcome this problem, most of the present high- speed data transmission topologies consume a significant amount of power to meet the minimum signal integrity requirements. One popular high-speed and low power standard used for point-to-point short-range data transmission is low voltage differential signaling (LVDS) [1–4]. It is defined in two separate industry standards: the generic electrical layer standard ANSI/TIA/EIA-644-1995 created by the tele- communication industry association—electronic industry association [1] and the IEEE 1596.3-1996 specific standard that is based on the physical layer defined for the scalable coherent interface (SCI) [2]. As in most point-to-point data communication systems, an LVDS data transfer system consists of a transmitter, a receiver, and a transmission media. Per the standard, the transmitter’s output signal should have a common-mode voltage between 1.125 and 1.375 V, and an amplitude swing between 250 and 450 mV [1–5]. These relatively low voltage swing requirements enable LVDS to consume less power compared to other signaling standards. Since data is sent differentially, the LVDS standard combines the ability to deliver high data rates while consuming low power with high noise immu- nity and low electromagnetic interference (EMI) [3–5]. Further, the standard increases the interface’s tolerance to H. W. Marar (&)  K. Abugharbieh Electrical Engineering Department, Princess Sumaya University for Technology, Amman, Jordan e-mail: hazemmarar@gmail.com H. W. Marar  A.-K. Al-Tamimi Computer Engineering Department, Yarmouk University, Irbid, Jordan 123 Analog Integr Circ Sig Process (2014) 79:1–13 DOI 10.1007/s10470-013-0224-6