444 IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 11, NOVEMBER 1998 Improvement of Hot Carrier Reliability with Deuterium Anneals for Manufacturing Multilevel Metal/Dielectric MOS Systems I. C. Kizilyalli, G. C. Abeln, Z. Chen, J. Lee, G. Weber, B. Kotzias, S. Chetlur, J. W. Lyding, and K. Hess Abstract—This paper discusses new experimental findings criti- cal for process integration of deuterium post-metal anneals to im- prove channel hot carrier reliability in manufacturing multilevel metal CMOS integrated circuits. Detailed account of the deu- terium process optimization experiments varying temperature, time, and ambient is given. Specifically, the first demonstration of the large hydrogen/deuterium isotope effect for multilevel metal/dielectric MOS systems is reported. Previous accounts of the isotope effect had been limited to CMOS structures with one-level of dielectric/metal and to about a 10 fold improvement in reliability. Deuterium, instead of hydrogen is introduced via an optimized post-metal anneal process to achieve a 50–100 fold improvement in transistor channel hot carrier lifetime. The benefits of the deuterium anneal are still observed even if the post- metal anneal is followed by the final SiN cap wafer passivation process. It is concluded that the deuterium post-metal anneal process is suitable for manufacturing high performance CMOS products and fully compatible with traditional integrated circuit processes. I. INTRODUCTION T HIS letter discusses new experimental findings critical for process integration of deuterium post-metal anneals to improve channel hot carrier reliability in manufacturing multilevel metal CMOS integrated circuits. Low temperature post-metal anneals in hydrogen ambients are used in MOS fabrication processes to passivate the silicon dangling bonds at the Si/SiO interface [1]–[5]. This process step is required from a CMOS operation and circuit stability viewpoint since silicon dangling bonds lead to nonideal capacitance–voltage ( – ) characteristics and reduced channel conductance [6]. However, under bias the MOS transistor performance can degrade as a result of channel hot (large kinetic energy) carriers (electrons and holes) simulating the desorption of the hydrogen that is passivating the dangling bonds at the Si/SiO interface or bound at the SiO /polysilicon interface. The hot carrier reliability concerns are further exacerbated with the ever ongoing miniaturization (scaling) efforts and added Manuscript received April 1, 1998; revised July 30, 1998. The work of K. Hess was supported by the Office of Naval Research and the Army Research Office. The work of J. Lee was supported by the Office of Naval Research and the Beckmann Institute for Advanced Science and Technology. I. C. Kizilyalli, B. Kotzias, and S. Chetlur are with the Lucent Technologies, Bell Laboratories, Orlando, FL 32819 USA (e-mail: ick@cmos.lucent.com). G. C. Abeln, Z. Chen, J. Lee, J. W. Lyding, and K. Hess are with the Beckman Institute, University of Illinois, Urbana, IL 61801 USA. G. Weber is with the Lucent Technologies, Bell Laboratories, Murray Hill, NJ 07974 USA. Publisher Item Identifier S 0741-3106(98)08496-1. dielectric/metallization layers in integrated circuits. Hence, a much needed advance in integrated circuit manufacturing is a methodology that enables reliable CMOS scaling by eliminating the undesirable effects of channel hot carriers. The dynamic hydrogen/deuterium isotope effect discovered by Lyding et al. [7] in NMOS transistors is the spectac- ular (10–50 fold) increase in time dependent channel hot carrier transistor (reliability) lifetime [6]–[8]. In the fabrica- tion sequence deuterium is introduced, instead of hydrogen, to the Si/SiO interface via a low temperature (400–450 C) post-metallization anneal process. The improvement is observed when a significant portion of the dangling bonds at the Si/SiO interface are passivated by deuterium rather than hydrogen. The chemistry of deuterium and hydrogen is virtually identical. Therefore, either atom is equally suitable for passivating the dangling bonds at interfaces [8]. This results in indistinguishable device function prior to hot carrier stress. The observed improvement in the degradation rates (lifetimes) in the transistors is a result of the large difference in the desorption rates of the two isotopes as discussed in [6]–[10]. The large disparity in the desorption yield of hydrogen and deuterium from Si(100)2 1 : H(D) surfaces in ultra-high vacuum was originally demonstrated using a scanning tun- neling microscope [11]–[14]. The large hydrogen/deuterium isotope effect in NMOS transistors [7] has been subsequently observed and verified by other laboratories [15], [16]. Stud- ies also indicate that transistors annealed in deuterium are much more resilient against plasma process induced damage (as quantified by Si/SiO interface trap generation and gate oxide leakage) [17]. Furthermore, stability of hydrogenated (deuterated) amorphous-silicon based solar cells [18], [19] and hydrogen (deuterium) terminated porous-silicon light emitting devices [20] has been found to improve with the isotopic substitution against degradation due to light and field exposure [21]. Clearly, the large hydrogen/deuterium isotope effect observed by [7] in CMOS transistors is a general property of the semiconductor device wear-out. For reasons outlined above there is a strong motivation to in- troduce the deuterium anneal process to CMOS manufacturing. However, there remains two major roadblocks for transfer of process to the factory floor. First, all modern CMOS technolo- gies require a minimum of three levels of dielectric/metal inter- connect process. Previously published accounts of deuterium anneals have been limited to single-level dielectric/metal sys- tems and about a factor of 10 improvement in hot carrier 0741–3106/98$10.00  1998 IEEE