Send Orders for Reprints to reprints@benthamscience.net Micro and Nanosystems, 2020, 12, 000-000 1 RESEARCH ARTICLE 1876-4029/20 $58.00+.00 ©2020 Bentham Science Publishers Improved Domino Logic Circuits and its Application in Wide Fan-in OR Gates Deepika Bansal 1,* , Bal Chand Nagar 2 , Brahamdeo Prasad Singh 1 and Ajay Kumar 3 1 Department of Electronics and Communication Engineering, Manipal University Jaipur, Rajasthan India; 2 Department of Electronics and Communication Engineering, National Institute of Technology Patna, India; 3 Department of Mecha- tronics Engineering, Manipal University Jaipur, Rajasthan, India Abstract: The main concern in efficient VLSI circuit designing is low-power consumption, high- speed and noise tolerance capability. In this paper, two efficient and high-performance topologies are proposed for cascaded domino logic using carbon nanotube MOSFETs (CN-MOSFETs). The first to- pology is designed to remove the intermediate charge sharing problem without any keeper circuit, whereas the second one holds the true logic level of the evaluation phase without any voltage drop for the next precharge phase. The proposed topologies are suitable for cascading of the high-performance domino circuits. A wide fan-in domino OR gate circuits are designed as a benchmark to verify the proposed topologies. The proposed domino circuits are tested and verified using Synopsys HSPICE simulator with 32nm CN-MOSFET technology provided by Stanford University. The power delay product of proposed DL-I and DL-II improves by 32.59 % and 40.98 % for 8-input OR gate as com- pared to standard logic respectively at a clock frequency of 500 MHz. The simulation results validate that the proposed circuits improve the performance of pseudo domino logic with respect to leakage power consumption, delay and unity noise gain. A R T I C L E H I S T O R Y Received: April 09, 2019 Revised: May 28, 2019 Accepted: June 25, 2019 DOI: 10.2174/1876402911666190716161631 Keywords: Dynamic logic, carbon nano-tubes, CN-MOSFET, keeper, stack, charge sharing. 1. INTRODUCTION The scaling of the complementary metal oxide semicon- ductor Field effect transistor (CMOS) technology in na- nometer scale leads to short channel effects, high power den- sity, high leakage currents and reliability issues [1]. Howev- er, high density, energy efficient, low power and battery op- erated applications are required in the area of medical and communication systems. Alternative nano-devices such as carbon nanotube MOSFETs (CN-MOSFETs) [2], single electron transistor (SET) [3] and quantum-dot cellular au- tomata (QCA) [4] are required to overcome these serious challenges at nanoscale technologies. Dynamic logic circuits are used for high-performance digital circuit design, which cannot be achieved in other log- ic styles such as static logic [5]. The high-performance cir- cuits are designed for wide fan-in logic gates [6], which are typically used in the register file for high-performance mi- croprocessor [7], read-circuit in memory, ternary content addressable memory, tag comparators, flash memories, wide multiplexers/de-multiplexers, and programmable logic arrays (PLAs) [8]. The domino circuits are implemented using *Address correspondence to this author at the Department of Electronics and Communication Engineering, Manipal University Jaipur, Rajasthan, 303007 India; Tel: +91 7742889057; E-mail: deepika.bansal@jaipur.manipal.edu CN-MOSFETs that reduce large area (due to the same size of p-channel and n-channel CN-MOSFETs) [9]. On the other hand, the main drawback of the dynamic circuits is that they are very sensitive to noise (due to lower noise margins) and consume high static power (due to charge leakage) as compared to static circuits. A keeper (or bleeder) topology is used in the convention- al method to improve the charge sharing problem [10]. It prevents undesired discharging at the dynamic node due to leakage current and charge sharing of the pull-down network (PDN) during the evaluation phase [11]. Keeper improves the noise performance and robustness by increasing the keeper ratio at the cost of delay and power dissipation. How- ever, these problems are a serious issue in wide fan-in logic gates due to a large number of leaky n-channel MOSFETs connected to the dynamic node. To overcome such issues, several keeper techniques are available in the literature given as follows: efficient keeper for domino [12], conditional keeper domino (CKD) [13], high speed domino (HSD) [14], leakage current replica keeper domino (LCRKD) [15], con- trolled keeper by current comparison domino (CKCCD) [16], and ultra-low power stacked (ULP-ST) domino logic [17]. Each keeper circuit [10-17] performs the similar task with dissimilarity in the execution. Some require more pow- er, some need a large area and some have more delay. In a few published articles, the keeper transistors are used to re-